A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

A method for bonding a first substrate with a second substrate, characterized in that the first substrate and/or the second substrate is/are thinned before the bonding.

A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

A method of manufacturing an electronic device includes: providing a vapor generating chamber that accommodates a heat transfer fluid; providing a substrate stage within the vapor generating chamber, the substrate stage including a seating surface and suction passages penetrating the substrate stage to be open to the seating surface; loading a substrate on the substrate stage, wherein electronic components are disposed on the substrate via bumps; generating at least a partial vacuum in the suction holes to suction-support the substrate on the seating surface; heating the heat transfer fluid to generate saturated vapor within the vapor generating chamber; and soldering the bumps using the saturated vapor.

A semiconductor package structure and forming method thereof; the semiconductor package structure includes a heat sink frame (2) and a lead frame (1), where the heat sink frame (2) is connected with a heat sink (4), a chip pad (21) of the lead frame (1) is adhered with a chip (3), and the heat sink (4) is connected to the chip (3) through a bonding material (5), and where the lead frame (1) is provided with a first lead (22), and the heat sink frame (2) is provided with a second lead (43) and a third lead (44). The method of forming the semiconductor package structure comprises: arranging the second lead (43) and the third lead (44) on the heat sink (4), and connecting the first lead (22) to the bottom electrode of the chip pad (21) to form a current input terminal; connecting three second lead (43) on the heat sink frame (2) to the top electrode of the chip (3) to form a current output terminal; welding the third lead (44) on the heat sink frame (2) with a conductive wire to form a current control terminal, thus greatly reducing the use of conductive wires, and thus heat loss; and after injection molding, colloids are exposed on of both sides of the semiconductor package structure, thus realizing double-sided heat dissipation, and improving heat dissipation of the semiconductor package structure.

An apparatus includes: a vapor generating chamber configured to accommodate a heat transfer fluid and to be filled with saturated vapor generated by the heat transfer fluid; a heater configured to heat the heat transfer fluid in the vapor generating chamber; a substrate stage configured to be movable upward or downward in the vapor generating chamber and to support a substrate on which an electronic device is mounted via a solder. The apparatus also includes at least one mesh plate extending in a horizontal direction in the vapor generating chamber. The at least one mesh plate includes a plurality of openings through which the vapor moves.

A three-dimensional (3D) integrated circuit (IC) package is disclosed that contains a plurality of encapsulated layers stacked upon each other without the use of a substrate(s). Each of the encapsulated layers contains an encapsulating material, a die, an interconnecting interface, and vertical vias. The encapsulating material forms the surfaces of an encapsulated layer and encapsulates the die. The interconnecting interface provides an interface at a surface of the encapsulated layer for the die to electrically connect to other dies or external components. The vertical vias provide a conduction path between interconnecting interfaces of different encapsulated layers.

A joined structure includes: a first member; and a second member that faces the first member and that is joined to the first member via a joining layer. The joining layer includes a metal material and a solder material, apart of the metal material has at least one pore, and the solder material is located in a part of an internal area of the at least one pore. Also disclosed is a joining method that makes it possible to produce the joined structure. Further disclosed is a joining material used in the joining method. The joining method makes it possible to achieve non-pressurization sintering processes while maintaining high precise thickness of a joining layer between the first layer and the second layer based on the spacer.

A zone heater assembly of a reflow solder tool includes a gas deflector having a single-layer structure. The single-layer structure may include one or more gas-permeating patterns through which a process gas is to flow from one or more gas outlets to a gas exhaust of the zone heater assembly. The one or more gas-permeating patterns in the single-layer structure promote uniformity of gas flow through the gas exhaust and into a heating zone of the reflow solder tool. The uniformity of the gas flow of the process gas enables convection heat provided by the process gas to be uniformly distributed across the heating zone. In this way, the gas deflector described herein may decrease hot spots and/or cold spots in the heating zone, which enables greater flexibility in placement of semiconductor package substrates on a conveyor device of the reflow solder tool.

A method of feeding underfill material to fill a space between a semiconductor die and a substrate onto which the semiconductor die has been bonded, the method comprises positioning a stencil over the semiconductor die. The stencil has an elongated slot extending adjacent to an edge of the semiconductor die. Underfill material is printed through the slot such that the underfill material falls through the slot onto the substrate next to the edge of the semiconductor die. Thereafter, the underfill material is heated such that the underfill material flows across the space between the semiconductor die and the substrate from the edge of the semiconductor die to an opposite edge thereof through capillary action.