An apparatus includes a first component layer. The component layer includes a first semiconductor device. The apparatus further includes a first hydrophilic layer and a first hydrophobic layer. The first hydrophobic layer is positioned between the first component layer and the first hydrophilic layer. The apparatus further includes a first contact extending through the first hydrophobic layer and the first hydrophilic layer.

A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly.

A method for manufacturing a display device includes preparing a circuit board including a drive circuit for driving a LED chip, forming a connecting electrode on the circuit board, forming an adhesive layer on the connecting electrode, adhering a terminal electrode of the LED chip on the adhesive layer and joining the connecting electrode and the terminal electrode by irradiating a laser light. The adhesive layer may be formed only on a upper surface of the connecting electrode.

This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.

Methods of bonding one or more dies to a substrate are provided herein. In some embodiments, a method of bonding one or more dies to a substrate includes: applying a material coating on the one or more dies or the substrate; placing the one or more dies on the substrate so that the one or more dies temporarily adhere to the substrate via surface tension or tackiness of the material coating; inspecting each of the one or more dies that are placed on the substrate for defects; and removing any of the one or more dies that are found to have defects.

A bonding method can include activating a first bonding layer of a first element for direct bonding to a second bonding layer of a second element. The bonding method can include, after the activating, providing a protective layer over the activated first bonding layer of the first element.

A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.

A flip-chip bonding method includes following operations. A wafer is provided with multiple semiconductor dies on an adhesive film held by a frame element. A semiconductor die is lifted up from the wafer by an ejector element. The semiconductor die is picked up with a collector element. The semiconductor die is flip-chipped with the collector element. An alignment check is performed to determine a position of the semiconductor die, so as to determine a process tolerance between a center of the collector element and a center of the semiconductor die. The semiconductor die with the collector element is transferred to a location underneath a bonder element based on the process tolerance of the alignment check. The semiconductor die is picked up from the collector element by the bonder element. The semiconductor die is bonded to a carrier by the bonder element.