A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

A liquid is supplied to a substrate and a chip component is arranged on the liquid. The substrate includes a first surface in which a rectangular mounting region is formed. The chip component includes a second surface having a rectangular shape which substantially coincides with the shape of the mounting region, and has an area substantially equal to that of the mounting region. The mounting region includes first and second regions. Wettability of the first region with respect to the liquid is higher than that of the second region with respect to the liquid. The first region is provided symmetrically with respect to a first central line passing through the middle of a pair of long sides and a second central line passing through the middle of a pair of short sides in the mounting region, and includes rectangular partial regions. The liquid is supplied to the first region.

A stacked wafer assembly is made by forming a grid of grooves corresponding to projected dicing lines in a face side of each of two wafers, thereby forming demarcated areas on the face side of each of the two wafers. One of the wafers is installed with demarcated areas face upwardly, and thereafter liquid is supplied to the demarcated areas in a quantity just enough to stay on upper surfaces of the demarcated areas without overflowing. The other wafer is placed over the one wafer with demarcated areas of the other wafer facing the respective demarcated areas of the one wafer, thereby bringing respective central positions of the facing demarcated areas of the wafers into self-alignment with each other under the surface tension of the liquid sandwiched between the facing demarcated areas. The liquid is removed to bring the wafers into intimate contact with each other.

A wafer-level semiconductor die attachment method includes placing a semiconductor die of a plurality of semiconductor dies at an initial placement position to overlap a sub-mount pad on a sub-mount of a pre-singulated wafer. A die pad of the semiconductor die comes in contact with a solder layer deposited over the sub-mount pad. The semiconductor die and the sub-mount include a plurality of die and sub-mount mating features, respectively. The solder layer is heated locally to temporarily hold the semiconductor die at the initial placement position. The pre-singulated wafer is reflowed, when each semiconductor die is temporarily held at the corresponding initial placement position. During reflow, each semiconductor die slides from the initial placement position and a contact is established between the corresponding plurality of die and sub-mount mating features. Thereby, each semiconductor die is permanently attached to the corresponding sub-mount.

A method of manufacturing an emissive LED display device, including the steps of forming a plurality of chips, each including at least one LED and, on a connection surface, a plurality of hydrophilic electric connection areas and a hydrophobic area; forming a transfer substrate including, for each chip, a plurality of hydrophilic electric connection areas and a hydrophobic area; arranging a drop of a liquid on each electric connection area of the transfer substrate and/or of each chip; and affixing the chips to the transfer substrate by direct bonding, using the capillary restoring force of the drops to align the electric connection areas of the chips with the electric connection areas of the transfer substrate.

A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements. The differential expansion compensation structure can be configured to compensate for differential expansion between the first and second semiconductor elements to reduce misalignment between at least the second and fourth contact features.

A method for direct bonding an electronic chip onto a substrate or another electronic chip, the method including: carrying out a hydrophilic treatment of a portion of, a surface of the electronic chip and of a portion of a surface of the substrate or of the other electronic chip; depositing an aqueous fluid on the portion of the surface of the substrate or of the second electronic chip; depositing the portion of the surface of the electronic chip on the aqueous fluid; drying the aqueous fluid until the portion of the surface of the electronic chip is rigidly connected to the portion of the surface of the substrate or of the other electronic chip: and during at least part of the drying of the aqueous fluid, emitting ultrasound into the aqueous fluid through the substrate or the other electronic chip.

Semiconductor packages and methods of forming the same are disclosed. Embodiments include forming a first recess in a first substrate, wherein a first area of an opening of the first recess is larger than a second area of a bottom of the first recess. The embodiments also include forming a first device, wherein a third area of a top end of the first device is larger than a fourth area of a bottom end of the first device. The embodiments also include placing the first device into the first recess, wherein the bottom end of the first device faces the bottom of the first recess, and bonding a sidewall of the first device to a sidewall of the first recess.

A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.