H01L2224/8022

METHOD AND APPARATUS TO CONTROL TRANSFER PARAMETERS DURING TRANSFER OF SEMICONDUCTOR DEVICES
20200105551 · 2020-04-02 · ·

An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position.

METHOD AND APPARATUS TO CONTROL TRANSFER PARAMETERS DURING TRANSFER OF SEMICONDUCTOR DEVICES
20200105551 · 2020-04-02 · ·

An apparatus includes a transfer mechanism to transfer an electrically-actuatable element directly from a wafer tape to a transfer location on a circuit trace on a product substrate. The transfer mechanism includes one or more transfer wires. Two or more stabilizers disposed on either side of the one or more transfer wires. A needle actuator is connected to the one or more transfer wires and the two or more stabilizers to move the one or more transfer wires and the two or more stabilizers to a die transfer position.

SEMICONDUCTOR PACKAGE UTILIZING A HYBRID BONDING PROCESS AND METHOD OF MANUFACTURING THE SAME
20240088105 · 2024-03-14 ·

A semiconductor package includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes a peripheral region having a groove and a bonding region that is disposed higher than the groove. The second semiconductor chip is disposed in the bonding region of the first semiconductor chip. The second semiconductor chip is directly electrically connected to the first semiconductor chip. The second semiconductor chip includes an overhang protruded from the bonding region. The overhang is spaced apart from a bottom surface of the groove. Thus, a bonding failure, which may be caused by particles generated during a cutting the wafer and adhered to the edge portion of the second semiconductor chip, between the first semiconductor chip and the second semiconductor chip might be avoided.

BONDING SYSTEM AND BONDING METHOD

Bonding system for bonding a second article to a first article, comprising an activation treatment device that comprises an object supporter that supports objects comprising the second article, and a particle beam source that activates a bonding surface of the second article by irradiating the objects with a particle beam, the objects being set on one treatment surface without being opposed to each other, followed by performing activation treatment by the particle beam source; and a bond device that brings the second article, of which the bonding surface is activated by the activation treatment device, into contact with the first article, to thereby bond the second article to the first article, wherein the object supporter supports the objects in a posture in which a portion formed of a plurality of kinds of materials comprising the bonding surface of the second article in the objects is exposed to the particle beam source.

BONDING SYSTEM AND BONDING METHOD

Bonding system that bonds each of a plurality of second articles to a first article, wherein each of the plurality of second articles is a chip comprising an uneven portion on a circumference closer to a bonding surface to be bonded to the first article, the bonding system comprises: a device for supplying a second article that supplies the plurality of second articles; a bond device that bonds the plurality of second articles to the first article by bringing the plurality of second articles into contact with the first article; and a device for transporting a second article that transports, to the bond device, at least one of the plurality of second articles supplied from the device for supplying a second article, and the device for transporting a second article comprises a holder for holding a second article that holds the uneven portion of the at least one second article.

BONDING LAYER AND PROCESS

A method includes providing a first bonding surface on a first substrate, the first bonding surface including a bonding layer that is thermally curable or photocurable. The method includes providing a second bonding surface on a second substrate. The method includes bonding the first substrate to the second substrate by making physical contact between the first bonding surface and second bonding surface. The method further includes applying thermal energy or light to the bonding layer.

Substrate bonding apparatus and method of manufacturing a semiconductor device
12002700 · 2024-06-04 · ·

According to one embodiment, there is provided a substrate bonding apparatus including a first chuck stage and a second chuck stage. The first chuck stage includes a first electromagnetic force generation unit. The first chuck stage is chuckable for a first substrate. The second chuck stage includes a second electromagnetic force generation unit. The second electromagnetic force generation unit faces the first electromagnetic force generation unit. The second chuck stage is chuckable for a second substrate.

Semiconductor-on-insulator with back side heat dissipation

Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Semiconductor-on-insulator with back side heat dissipation

Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Bonding system and bonding method

Bonding system that bonds each of a plurality of second articles to a first article, wherein each of the plurality of second articles is a chip comprising an uneven portion on a circumference closer to a bonding surface to be bonded to the first article, the bonding system comprises: a device for supplying a second article that supplies the plurality of second articles; a bond device that bonds the plurality of second articles to the first article by bringing the plurality of second articles into contact with the first article; and a device for transporting a second article that transports, to the bond device, at least one of the plurality of second articles supplied from the device for supplying a second article, and the device for transporting a second article comprises a holder for holding a second article that holds the uneven portion of the at least one second article.