A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

A semiconductor package includes a plurality of first semiconductor structures that are stacked on a package substrate and are offset from each other in a first direction, and a plurality of first adhesive layers disposed between the first semiconductor structures. Each of the first semiconductor structures includes a first sub-chip and a second sub-chip in contact with a part of a top surface of the first sub-chip. The first adhesive layers are disposed between and are in contact with the first sub-chips. The first adhesive layers are spaced apart from the second sub-chips. A thickness of each of the first adhesive layers is less than a thickness of each of the second sub-chips. The thickness of the second sub-chip is in a range of about 13 μm to about 20 μm.

Embodiments of methods for producing direct bonded structures and methods for forming direct bonded structures are disclosed. The direct bonded structures may include elements comprising active electronics, microelectromechanical systems, optical elements, and so forth.

Embodiments of methods for producing direct bonded structures and methods for forming direct bonded structures are disclosed. The direct bonded structures may include elements comprising active electronics, microelectromechanical systems, optical elements, and so forth.

An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.

An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

An image sensor includes a sensor chip and a logic chip. The sensor chip includes a first substrate, an upper bonding layer, a first wiring layer, and the logic chip includes a second substrate, a lower bonding layer, a second wiring layer. The upper and lower bonding layers contact each other, with the upper bonding layer including an upper dielectric layer, an upper conductive pad, an upper shield structure, and an upper wiring line, and the lower bonding layer including a lower dielectric layer, a lower conductive pad, a lower shield structure, and a lower wiring line. The upper wiring line, upper conductive pad, and upper shield structure being one body, and the lower wiring line, lower conductive pad, and lower shield structure being one body, the upper and lower conductive pads overlap and contact each other, and the upper and lower wiring lines overlap and contact each other.