A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.

A wafer level packaging method includes the following steps. A first wafer is bonded over a second wafer. A first grinding process on the first wafer is performed, to remove an upper chamfered edge of the first wafer and reduce a thickness of the first wafer. A trimming process is performed on the first wafer, to remove a lower chamfered edge of the first wafer to form a trimmed first wafer. A second grinding process is performed on the trimmed first wafer, to reduce a thickness of the trimmed first wafer.

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

A power electronic system includes a semiconductor module that includes a power electronic substrate having opposite first and second sides, power semiconductor die arranged over the second side of the substrate, and an encapsulation encapsulating the power semiconductor dies. The first side of the power electronic substrate is at least partially exposed from a first side of the encapsulation. The semiconductor module is arranged over an exterior surface of a wall of a cooler configured for fluidic cooling, such that the first side of the power electronic substrate faces the wall. The cooler includes cooling structures arranged on an interior surface of the wall. A first portion of the wall directly below the power electronic substrate has a first wall thickness and a second portion of the wall laterally next to the first portion has a second wall thickness, the first wall thickness being greater than the second wall thickness.

A power module is designed with balanced current flow for each power switch in parallel so that every power switch has a similar current path length. The power module can include a first plurality of power switches electrically coupled to a first region and a second plurality of power switches electrically coupled to a second region. A first plurality of conductive clips are configured to conduct a first plurality of currents and a second plurality of conductive clips are configured to conduct a second plurality of currents. The power module can include a first lead frame configured to apply positive voltage to the first region, a second lead frame configured to conduct current from the second region and a third lead frame configured to conduct current from the third region.

A semiconductor power entity including a first laminate layer; a second laminate layer; an isolation layer arranged between the first laminate layer and the second laminate layer; a first metal layer arranged at a first laminate upper main face of the first laminate layer and a second metal layer arranged at a first laminate lower main face of the first laminate layer; a third metal layer arranged at a second laminate upper main face of the second laminate layer and a fourth metal layer arranged at a second laminate lower main face of the second laminate layer; and a connection metal layer embedded in the isolation layer between the first laminate layer and the second laminate layer, the connection metal layer forming an electrical connection with the second metal layer and the third metal layer.

A method for fabricating a semiconductor device includes: providing a substrate; applying a sinter paste layer to the substrate; placing a semiconductor die on or above the sinter paste layer; performing a sintering process to convert the sinter paste layer to a sintered layer; and applying a protective layer by atomic layer deposition or by plasma-enhanced chemical layer deposition onto the semiconductor die and the sintered layer.

A power module includes: a first substrate having an outer surface and an inner surface, the first substrate extending from a first longitudinal end toward a second longitudinal end; a semiconductor die coupled to the inner surface of the first substrate; and a second substrate having an outer surface and an inner surface, the semiconductor die being coupled to the inner surface of the second substrate, the second substrate extending from a first longitudinal end toward a second longitudinal end, wherein the first longitudinal end of the first substrate is longitudinally offset from the first longitudinal end of the second substrate.