A display device made of a TFT substrate and a driver IC is configured to eliminate bad connection between them. On the driver IC connected to the TFT substrate, a first principal surface has first bumps formed along a first side having a first edge and second bumps formed along a second side opposite to the first side and having a second edge. The TFT substrate has first terminals and second terminals connected to the first and the second bumps, respectively. On a cross section taken perpendicularly to the first and the second sides, the first principal surface has a first area between the first and the second bumps and a second area between the second bumps and the second edge. The first and the second areas are bent toward the TFT substrate.

A semiconductor package may be provided. The semiconductor package may include a substrate having a first surface over which bond fingers are arranged, the other surface facing away from the first surface and over which ball lands are arranged, and terminals which are respectively formed over the bond fingers. The semiconductor package may include a semiconductor chip disposed over the first surface of the substrate, and having an active surface facing the first surface and over which bonding pads are arranged. The semiconductor package may include bumps respectively formed over the bonding pads of the semiconductor chip, and including pillars and layers which are formed over first side surfaces of the pillars and are joined with the terminals of the substrate.

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

A semiconductor package may be provided. The semiconductor package may include a substrate having a first surface over which bond fingers are arranged, the other surface facing away from the first surface and over which ball lands are arranged, and terminals which are respectively formed over the bond fingers. The semiconductor package may include a semiconductor chip disposed over the first surface of the substrate, and having an active surface facing the first surface and over which bonding pads are arranged. The semiconductor package may include bumps respectively formed over the bonding pads of the semiconductor chip, and including pillars and layers which are formed over first side surfaces of the pillars and are joined with the terminals of the substrate.

The invention relates to a chip arrangement (18) comprising a terminal substrate (12) and a plurality of semiconductor substrates (1) which are arranged on the terminal substrate, in particular chips, wherein terminal faces (5) arranged on a contact surface of the chips (1) are connected to terminal faces on a contact surface (14) of the terminal substrate (12), wherein the chips (1) extend parallel with a lateral edge and transversally with their contact surface to the contact surface of the terminal substrate (12), wherein vias (13) are arranged in the terminal substrate, which connect external contacts (15) arranged on an external contact side to terminal faces formed as internal contacts (14) on the contact surface of the terminal substrate, wherein terminal faces of the chips, which are arranged adjacent to the lateral edge, are connected to the internal contacts of the terminal substrate by way of a re-melted solder material deposit (16). Furthermore, the invention relates to a method for producing a chip arrangement (18).

A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate.

A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap. Accordingly, after the first and second semiconductor structures are bonded together, at least 99.5% of the active photodetector are electrically connected with their respective RICPs.

A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.

The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance.

Provided is an anisotropic conductive adhesive in which excellent optical characteristics and heat dissipation characteristics are obtainable. The anisotropic conductive adhesive contains conductive particles each comprising a metal layer having Ag as a primary constituent formed on an outermost surface of a resin particle, solder particles having a smaller average particle diameter than the conductive particles, reflective insulating particles having a smaller average particle diameter than the solder particles and a binder into which the conductive particles solder particles and reflective insulating particles are dispersed. The conductive particles and the reflective insulating particles efficiently reflect light, thereby improving light-extraction efficiency of an LED mounting body. Additionally, inter-terminal solder bonding of the solder particles during compression bonding increases contact area between opposing terminals, thereby enabling achievement of high heat dissipation characteristics.