A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.

An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

A method is provided. The method includes one or more of conditioning one or more die pads of a singular die, applying a nickel layer to the one or more die pads, applying a gold layer over the nickel layer, applying a solder paste over the gold layer, applying one or more solder balls to the solder paste, and mating the one or more solder balls to one or more bond pads of another die, a printed circuit board, or a substrate.

A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.

A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling cavity, and a coupling structure located at least partially in the at least one coupling cavity and electrically contacting the at least one electric contact structure with the chip carrier.

An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): ##STR00001##
wherein R.sup.1 represents an electron-donating group.

An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): ##STR00001##
wherein R.sup.1 represents an electron-donating group.

A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by evaporating a vaporizable portion (1250) of the solder connection. Other features are also provided.