Disclosed herein are integrated circuit (IC) packages with temperature sensor traces, and related systems, devices, and methods. In some embodiments, an IC package may include a package substrate and an IC die disposed on the package substrate, wherein the package substrate includes a temperature sensor trace, and an electrical resistance of the temperature sensor trace is representative of an equivalent temperature of the temperature sensor trace.

Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA) package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is application of solder to the RGA interposer. Technical solutions described herein provide processes and equipment for application of solder and formation of solder balls to connect an RGA interposer to a BGA package.

An array substrate includes a driver, a glass substrate having a driver mounting section where the driver is mounted, an anisotropic conductive material that is interposed between the driver and driver mounting section so as to electrically connect both and that at least includes a binder made of a thermosetting resin and conductive particles in the binder, and a heat supply part provided on at least the driver mounting section of the glass substrate for supplying heat to the anisotropic conductive material.

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure relate to separating an integrated circuit (IC) structure from an adjacent chip. An IC structure according to embodiments of the disclosure may include: a semiconductor region including an interconnect pad positioned thereon, the interconnect pad electrically connected to a solder bump; and an ohmic heating wire positioned within the semiconductor region and in thermal communication with the interconnect pad, wherein the ohmic heating wire is configured to be heated above a melting temperature of the solder bump.

A bonded assembly may be formed by providing a wafer comprising at least a first packaging substrate and a second packaging substrate in a low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient while performing a first substrate-treatment process on the first packaging substrate in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; and performing a second plasma package-treatment process on the second semiconductor package while performing a second substrate-treatment process on the second packaging substrate and while bonding the first semiconductor package to the first packaging substrate.

A bonded assembly may be formed by providing at least a first packaging substrate in a low-oxygen ambient; providing at least a first semiconductor package in the low-oxygen ambient; performing a first plasma package-treatment process on the first semiconductor package in the low-oxygen ambient by directing at least one first plasma jet to first solder material portions bonded to the first semiconductor package; and bringing the first solder material portions onto, or in proximity to, first substrate-side bonding structures located on the first packaging substrate while the at least one first plasma jet is directed to the first solder material portions. The first substrate-side bonding structures are treated with the first plasma jet. The first semiconductor package is bonded to the first packaging substrate while, or after, the first substrate-side bonding structures are treated with the first plasma jet.

An array substrate includes a driver, a glass substrate having a driver mounting section where the driver is mounted, an anisotropic conductive material that is interposed between the driver and driver mounting section so as to electrically connect both and that at least includes a binder made of a thermosetting resin and conductive particles in the binder, and a heat supply part provided on at least the driver mounting section of the glass substrate for supplying heat to the anisotropic conductive material.