An electronic device, a package structure and an electronic manufacturing method are provided. The electronic device includes a substrate, a first bump, a second bump and a first reflowable material. The first bump is disposed over the substrate, and has a first width. An end portion of the first bump defines a first recess portion. The second bump is disposed over the substrate, and has a second width less than the first width. The first reflowable material is disposed on the first bump and extends in the first recess portion.

A light emitting diode (LED) array is formed by bonding an LED substrate to a backplane substrate via fitted nanotube interconnects. The backplane substrate may include circuits for driving the LED array. The LED substrate may be a chip or wafer, and may include one or more LED devices. The LED substrate is positioned above the backplane substrate, such that a LED device of the LED substrate is aligned to a corresponding circuit in the backplane substrate. Each of the fitted interconnects electrically connect a LED device to the corresponding circuit of the backplane substrate.

In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

An electronic device for interconnection with an integrated circuit device is provided. The electronic device includes an interconnection surface configured to oppose the integrated circuit device with an interconnect structure disposed therebetween. The electronic device also includes at least one electronic device contact pad disposed on the interconnection surface for bonding to the interconnect structure. The at least one electronic device contact pad has at least one 3-dimensional projection configured to extend from the electronic device contact pad toward the integrated circuit device. The at least one 3-dimensional projection is configured to aid in bonding the electronic device contact pad to the interconnect structure to electrically couple the electronic device to the integrated circuit device.

A light emitting diode (LED) array is formed by bonding an LED substrate to a backplane substrate via magnetized interconnects. The backplane substrate may include circuits for driving the LED array, and each of the magnetized interconnects electrically connect a LED device to a corresponding circuit of the backplane substrate. The magnetized interconnects may be formed by electrically connecting first structures protruding from the backplane substrate to second structures protruding from the LED substrate. At least one of the first structure and the second structure includes ferromagnetic material configured to secure the first structure to the second structure.

A backplane (0) and a fabrication method therefor, a chip (01) bonding method, and a display device. The backplane (0) comprises: a base substrate (10); and conductive connection tubes (20) located on the base substrate (10). One end of each conductive connection tube (20) is connected to the base substrate (10), and the side walls of the conductive connection tubes (20) are provided with openings that penetrate said side walls. During the process of bonding the chip (01) to the backplane (0), when the conductive connection tubes (20) are heated, air within inner cavities of the conductive connection tubes (20) can be discharged by means of the openings on the side walls of the conductive connection tubes (20), which helps to ensure the reliability of the bonding between the chip (01) and the backplane (0).

A method for electrical connection by hybridisation of a first component with a second component. The method comprises the following steps: forming pads of ductile material in contact respectively with connection zones of the first component; forming inserts of conductive material in contact with the connection zones of the second component; forming hybridisation barriers arranged between the inserts and electrically insulated from each other, the first and second hybridisation barriers serving as a barrier by containing the deformation of the pads of ductile material during the connection of the connection zones of the first component with those of the second component. The disclosure also relates to an assembly of two connected components.

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

A stamp for micro-transfer printing includes a support having a support stiffness and a support coefficient of thermal expansion (CTE). A pedestal layer is formed on the support, the pedestal layer having a pedestal layer stiffness that is less than the support stiffness and a pedestal layer coefficient of thermal expansion (CTE) that is different from the support coefficient of thermal expansion (CTE). A stamp layer is formed on the pedestal layer, the stamp layer having a body and one or more protrusions extending from the body in a direction away from the pedestal layer. The stamp layer has a stamp layer stiffness that is less than the support stiffness and a stamp layer coefficient of thermal expansion that is different from the support coefficient of thermal expansion.

Embodiments relate to the design of a device capable of maintaining the alignment an interconnect by resisting lateral forces acting on surfaces of the interconnect. The device comprises a first body comprising a first surface with a nanoporous metal structure protruding from the first surface. The device further comprises a second body comprising a second surface with a locking structure to resist a lateral force between the first body and the second body during or after assembly of the first body and the second body.