Disclosed are a driving backplane and a display apparatus, including: a base substrate, a first conducting layer disposed on one side of the base substrate, a second conducting layer disposed on one side, facing away from the base substrate, of the first conducting layer, and a first insulating layer disposed between the first conducting layer and the second conducting layer, where the second conducting layer includes a plurality of pads, and each pad is connected with the first conducting layer through at least two first via holes.

Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.

A device transfer substrate includes a plurality of recesses, wherein each of the plurality of recesses includes a first region having a shape of a first figure, a second region having a shape of a second figure, and an overlapping region formed as a portion of the first region partially overlaps a portion of the second region, wherein a maximum width of the overlapping region in a direction intersecting with a straight line passing through a center of the first figure and a center of the second figure is less than a diameter or a diagonal length of the first figure and less than a diameter or a diagonal length of the second figure.

A semiconductor structure includes a first substrate including a first pad thereover, a second substrate including a bump thereover and a dielectric material. The first pad includes an inner portion and an outer portion being higher than and surrounding the inner portion. The bump is bonded to the inner portion and surrounded by the outer portion. The dielectric material is disposed between the first substrate and the second substrate to encapsulate the first pad and the bump.

A display apparatus is provided. The display apparatus includes a display substrate and a plurality of pads arranged above the display substrate. Each of the plurality of pads includes a first conductive layer, at least a portion of which is covered by an insulating film, a second conductive layer arranged above the first conductive layer, and a clamping portion formed in the second conductive layer.

A wiring substrate includes a first insulating layer including a first through-hole formed through the first insulating layer in a thickness direction, a wiring layer formed on a lower surface of the first insulating layer, and a via wiring filled in the first through-hole and connected to the wiring layer, the via wiring having such a shape that it gradually becomes thinner from one side close to the lower surface of the first insulating layer toward the other side close to an upper surface of the first insulating layer, the via wiring including a first recess formed in an upper end surface of the via wiring. An upper end portion of the via wiring is an electrode pad for electric connection with an electronic component.

This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.

Provided is a semiconductor package including: a first substrate having a first electrode pad and a first protective layer in which a cavity is formed; a first bump pad arranged in the cavity and connected to the first electrode pad; a second substrate facing the first substrate and having a second bump pad; and a bump structure in contact with the first bump pad and the second bump pad, wherein the first electrode pad has a trapezoidal shape, and the first bump pad has a flat upper surface and an inclined side surface extending along a side surface of the first electrode pad.

Contact bumps between a contact pad and a substrate can include a rough surface that can mate with the material of the substrate of which may be flexible. The rough surface can enhance the bonding strength of the contacts, for example, against shear and tension forces, especially for flexible systems such as smart label and may be formed via roller or other methods.

In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.