A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first plurality of openings is separated from each other by portions of the metal pad, with the portions of the metal pad interconnected to form a continuous metal region.

A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.

A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure.

A submount for connecting a semiconductor device to an external circuit, the submount comprising: a planar substrate formed from an insulating material and having relatively narrow edge surfaces and first and second relatively large face surfaces; at least one recess formed along an edge surface; a layer of a conducting material formed on a surface of each of the at least one recess; a first plurality of soldering pads on the first face surface configured to make electrical contact with a semiconductor device; and electrically conducting connections each of which electrically connects a soldering pad in the first plurality of soldering pads to the layer of conducting material of a recess of the at least one recess.

A jointed body that has been solid-phase jointed at normal temperature and that has a non-conventional structure is presented. The jointed body is formed by solid-phase joining a first jointed member to a second jointed member, and has a junction interface between the first member and the second member. This jointed body includes an average crystal grain size in a near interface structure that constitutes a near interface area having a total width of 20 micrometers and extending at both sides of the junction interface as a center is 75-100% of an average crystal grain size in an around interface structure that constitutes around interface areas located at both outer sides of the near interface area. In the jointed body, the near interface structure after the joining is almost the same as the structure before the joining, allowing the jointed body to exert similar characteristics to the jointed members.

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

A display device includes: a display substrate having an active area, which includes a pixel array, and a peripheral area around the active area; a driving chip on the display substrate; and a conductive combination member connecting the display substrate to the driving chip, wherein the display substrate includes: a first signal line in the peripheral area to transfer a driving signal from the driving chip to the active area, the first signal line including a first connection pad; a second connection pad at a different layer from the first connection pad and overlapping at least a portion of the first signal line; and a contact member contacting the first connection pad, the second connection pad, and the conductive combination member.

A conducting package structure includes a substrate and a conducting material. The conducting material is formed to a first patterned structure. The first patterned structure has a first surface which is connected to the substrate and a patterned second surface opposite to the first surface.

A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and a die pad and a bottom metal frame portion having apertures positioned lateral to the die pad. The protruding features and apertures are similarly sized and alignable. A flipped integrated circuit (IC) die having a bottomside and a topside including circuitry connected to bond pads having solder balls on the bond pads is mounted with its topside onto the top metal frame portion. The top metal frame portion is aligned to the bottom metal frame portion so that the protruding features are aligned to the apertures. The bottomside of the IC die is pressed with respect to a top surface of the bottom frame portion, wherein the protruding features penetrate into the apertures.