A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.

A voltage regulator having a coil inductor is integrated or embedded in a system-on-chip (SOC) device. The coil inductor is fabricated on an inductor wafer with through vias, and the inductor wafer is joined with an SOC wafer for integration with the SOC device.

In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.

A method is disclosed for electrically bonding a first semiconductor component to a second semiconductor component, both components including arrays of contact areas. In one aspect, prior to bonding, layers of an intermetallic compound are formed on the contact areas of the second component. The roughness of the intermetallic layers is such that the intermetallic layers include cavities suitable for insertion of a solder material in the cavities, under the application of a bonding pressure, when the solder is at a temperature below its melting temperature. The components are aligned and bonded, while the solder material is applied between the two. Bonding takes place at a temperature below the melting temperature of the solder. The bond can be established only by the insertion of the solder into the cavities of the intermetallic layers, and without the formation of a second intermetallic layer.

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

A cell of fluidic assembly of microchips on a substrate, including: a base having its upper surface intended to receive the substrate; a body laterally delimiting a fluidic chamber above the substrate; and a cover closing the fluidic chamber from its upper surface, wherein the body comprises first and second nozzles respectively emerging onto opposite first and second lateral edges of the fluidic chamber, each of the first and second nozzles being adapted to injecting and/or sucking in a liquid suspension of microchips into and/or from the fluidic chamber, in a direction parallel to the mean plane of the substrate.

A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion.

A preparation method of a backplane includes: forming an insulating structure layer having a groove on a base substrate by a mask exposure process, the groove being used for accommodating a metal trace; and repeating a metal sub-layer forming step including an ashing process and a wet etching process multiple times to form the metal trace positioned in the groove.

This application relates to semiconductor manufacturing, and more particularly to an interconnect structure for semiconductors with an ultra-fine pitch and a forming method thereof. The forming method includes: preparing copper nanoparticles using a vapor deposition device, where coupling parameters of the vapor deposition device are adjusted to control an initial particle size of the copper nanoparticles; depositing the copper nanoparticles on a substrate; invertedly placing a chip with copper pillars as I/O ports on the substrate; and subjecting the chip and the substrate to hot-pressing sintering to enable the bonding.

A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.