This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.

A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.

A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

A semiconductor package according to an embodiment of the present invention Includes: a lead frame comprising a pad and a lead spaced apart from the pad by a regular interval; a semiconductor chip adhered on the pad; and a clip structure electrically connecting the semiconductor chip and the lead, wherein an one end of the clip structure connected to the semiconductor chip inclines with respect to upper surfaces of chip pads of the semiconductor chip and is adhered to the upper surfaces of the chip pads of the semiconductor chip. A semiconductor package according to another embodiment of the present invention includes: a semiconductor chip comprising one or more chip pads; one or more leads electrically connected to the chip pads; and a sealing member covering the semiconductor chip, wherein an one end of the lead inclines with respect to one surface of the chip pad and is adhered to the chip pad and an other end of the lead is exposed to the outside of the sealing member.

A package includes a first and a second package component. The first package component includes a first metal trace and a second metal trace at the surface of the first package component. The second metal trace is parallel to the first metal trace. The second metal trace includes a narrow metal trace portion having a first width, and a wide metal trace portion having a second width greater than the first width connected to the narrow metal trace portion. The second package component is over the first package component. The second package component includes a metal bump overlapping a portion of the first metal trace, and a conductive connection bonding the metal bump to the first metal trace. The conductive connection contacts a top surface and sidewalls of the first metal trace. The metal bump is neighboring the narrow metal trace portion.

A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

A method includes patterning a cavity through a first passivation layer of a first package component, the first package component comprising a first semiconductor substrate and bonding the first package component to a second package component. The second package component comprises a second semiconductor substrate and a second passivation layer. Bonding the first package component to the second package component comprises directly bonding the first passivation layer to the second passivation layer; and reflowing a solder region of a conductive connector disposed in the cavity to electrically connect the first package component to the second package component.

A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner.

A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.