A wiring board includes: an insulating layer; and a wiring layer including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer. A recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and the recess portion is filled with the insulating layer.

A bump structure includes a pad. A passivation layer covers a perimeter of the pad. The passivation layer includes an opening exposing an area of the pad. A first portion is disposed on the pad. The first portion includes a top surface and a sidewall. A second portion covers the top surface and entire sidewall of the first portion.

A bump structure includes a pad. A passivation layer covers a perimeter of the pad. The passivation layer includes an opening exposing an area of the pad. A first portion is disposed on the pad. The first portion includes a top surface and a sidewall. A second portion covers the top surface and entire sidewall of the first portion.

Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive particles.

An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

A method including: attaching a plurality of conductive tracks to at least one surface of a substrate, depositing a coating comprising at least one halo-hydrocarbon polymer on the at least one surface of the substrate, and soldering through the coating.

An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane.

An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.