The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.

A wiring substrate includes a first wiring substrate, a first insulation layer covering the first wiring layer, a second insulation layer stacked on the first insulation layer, and a cavity extending through the second insulation layer and exposing a portion of the upper surface of the first insulation layer. The cavity includes an opening, which is defined by an upper portion of a stepped inner wall surface of the second insulation layer, and a recess, which is defined by a lower portion of the stepped inner wall surface that contacts the upper surface of the first insulation layer. The recess is wider than the opening. An electronic component is mounted on the upper surface of the first insulation layer. The opening and the recess are filled with a third insulation layer that covers the electronic component and the second insulation layer.

A wiring substrate includes a first wiring substrate, a first insulation layer stacked on the first wiring layer, and second and third insulation layers sequentially stacked on the first insulation layer. An electronic component is mounted on the first insulation layer in a cavity extending through the second and third insulation layers. The cavity is filled with a fourth insulation layer that entirely covers an upper surface of the third insulation layer and covers the electronic component. A second wiring layer is incorporated in the second and third insulation layers and electrically connected to the first wiring layer. The second wiring layer is electrically connected to a third wiring layer, which is stacked on the fourth insulation layer, by a first via wiring extending through the second and third insulation layers.

A wiring substrate used for improvement in manufacturing efficiency of a semiconductor device includes a support body having transparency; an adhesive layer disposed on a main surface of the support body, the adhesive layer including a peeling layer which contains a third resin which is decomposed by light irradiation and a protective layer which is disposed on the peeling layer and contains a fourth resin; and a laminate disposed on the adhesive layer, the laminate including a first resin layer, a second resin layer disposed on the first resin layer, and a wiring pattern disposed at least between the first resin layer and the second resin layer. Accordingly, the semiconductor chip and the wiring substrate which is the external connection member can be separately manufactured, thereby improving manufacturing efficiency of the semiconductor device.

The invention concerns a method of flip-chip assembly between first (1) and second (2) components each comprising connection pads (11, 21) on one of the faces of same, referred to as assembly faces, which involves transferring the components onto each other via the assembly faces of same in such a way as to create electrical interconnections between the pads of the first and second components. The invention involves transforming the copper oxide into copper by UV annealing, very locally, in the gap between the components, at least around the areas adjacent to the connection pads. The method according to the invention can be used for any component that is transparent to UV rays, including for substrates made from a plastic material such as substrates made from PEN or PET. The invention also concerns the assembly of two components obtained by the method.

An active substrate includes a plurality of active components distributed over a surface of a destination substrate, each active component including a component substrate different from the destination substrate, and each active component having a circuit and connection posts on a process side of the component substrate. The connection posts may have a height that is greater than a base width thereof, and may be in electrical contact with the circuit and destination substrate contacts. The connection posts may extend through the surface of the destination substrate contacts into the destination substrate connection pads to electrically connect the connection posts to the destination substrate contacts.

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).

An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane.

A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other.