The present disclosure provides a chip packaging method and a chip structure. The chip packaging method comprises: providing a wafer, and forming a protective layer on a wafer active surface of the wafer; cutting and separating the wafer to form a die; providing a metal structure, the metal structure including at least one metal unit; adhering the die and the metal structure onto a carrier; and forming a molding layer. The chip structure comprises: at least one die; a protective layer; a metal unit, the metal unit including at least one metal feature; and a molding layer, encapsulating the at least one die and the metal unit, and the chip structure is connected with an external circuit through the at least one metal feature. By adopting a plurality of metal features of the metal unit, the present disclosure achieves improved packaging performance brought by different metal features; and the wafer active surface is provided with the protective layer in the present disclosure, so that a step of applying an insulating layer after the formation of the molding layer is omitted.

An electrical device with printed interconnects between packaged integrated circuit components and a substrate as well as a method for printing interconnects between packaged integrated circuit components and a substrate are disclosed. An electrical device with printed interconnects may include a dielectric layer forming a continuous surface between a substrate and a terminal face of an integrated circuit component. The electrical device may further include interconnects formed from a layer of material printed across the continuous surface formed by the dielectric layer to connect electrical terminals on the substrate to electrical terminals on the terminal face of the integrated circuit component.

A method of manufacturing an electronic-component-embedded substrate includes forming a power-supplying metal layer on a base, forming through electrodes that are to be connected to the power-supplying metal layer on the power-supplying metal layer by an electrolytic plating method, forming a first wiring line by patterning the power-supplying metal layer, forming an interlayer insulating layer such that the interlayer insulating layer covers a portion of the first wiring line, and forming a second wiring line on at least a portion of the first wiring line and a portion of the interlayer insulating layer such that the second wiring line crosses, on the interlayer insulating layer, a portion of the first wiring line.

A method of manufacturing an electronic-component-embedded substrate includes forming a power-supplying metal layer on a base, forming through electrodes that are to be connected to the power-supplying metal layer on the power-supplying metal layer by an electrolytic plating method, forming a first wiring line by patterning the power-supplying metal layer, forming an interlayer insulating layer such that the interlayer insulating layer covers a portion of the first wiring line, and forming a second wiring line on at least a portion of the first wiring line and a portion of the interlayer insulating layer such that the second wiring line crosses, on the interlayer insulating layer, a portion of the first wiring line.

The invention relates to a method (110) for producing an electrically conductive connection (112, 112′) on a substrate (114), comprising the following steps: a) providing a substrate (114), wherein the substrate (114) is configured for receiving an electrically conductive connection (112, 112′); b) providing a reservoir of an electrically conductive liquid alloy, wherein the reservoir has a surface at which the alloy has an insulating layer; c) providing a capillary (120) configured for taking up the electrically conductive liquid alloy; d) penetrating of a tip (122) of the capillary (120) under the surface of the reservoir and taking up of a portion of the alloy from the reservoir; and e) applying the portion of the alloy at least partly to the substrate (114) in such a manner that an electrically conductive connection (112, 112′) is formed from the alloy on the substrate (114), wherein the alloy remains on the substrate (114) by adhesion.

The invention furthermore relates to a method for producing a microelectronic device (124) and to a microelectronic device (124), in particular a transistor (130).

Provided is a semiconductor device manufacturing method through which semiconductor elements are multilayered through the lamination of wafers in which the semiconductor elements are fabricated, the method thereof being suited for efficiently manufacturing semiconductor devices while realizing a large number of wafer lamination. With the method of the present invention, at least two wafer laminates are formed, each wafer laminate having a laminated structure, the structure including a plurality of wafers including an element forming surface and a back surface, with the element forming surface and the back surface facing between adjacent wafers; a through electrode is formed in each wafer laminate with the through electrode extending through an inside of the wafer laminate, from an element forming surface side of a first wafer located at one end of the wafer laminate in a lamination direction, to a position exceeding an element forming surface of a second wafer located at another end; the through electrode is exposed at a back surface side of the second wafer by grinding the back surface side thereof; and two wafer laminates that have been subjected to this exposing step are laminated and bonded while electrically connecting the through electrodes between the wafer laminates.

The present application discloses a semiconductor device with protection layers for reducing the metal to silicon leakage and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a first conductive feature positioned in the first die, a second die positioned on the first die, a first mask layer positioned on the second die, a conductive filler layer positioned along the first mask layer and the second die, extending to the first die, and contacting the first conductive feature, isolation layers positioned between the conductive filler layer and the first die and between the conductive filler layer and the second die, and protection layers positioned between the conductive filler layer and the first mask layer and covering upper portions of the isolation layers.

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.