Patent classifications
H01L2224/82385
Assembly substrates including through hole vias and methods for making such
Various embodiments are related to substrates having one or more well structures with a trapezoidal cylinder shaped through hole via extending from the bottom of the well structure though the substrate.
SUBSTRATE, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONIC SUBSTRATE
A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion.
SEMICONDUCTOR MODULE
A semiconductor module includes: a first insulating plate; a second insulating plate is arranged above the first insulating plate; a first semiconductor device provided on an upper surface of the first insulating plate; a second semiconductor device provided on a lower surface of the second insulating plate; an insulating substrate including a third insulating plate arranged between the first insulating plate and the second insulating plate, and a conductor provided on the third insulating plate and connected to the first and second semiconductor devices; and sealing resin sealing the first and second semiconductor devices and the insulating substrate, wherein a withstand voltage of the third insulating plate is lower than withstand voltages of the first and second insulating plates.
Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement
A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.
Heat exchangers with plates having surface patterns for enhancing flatness and methods for manufacturing same
A heat exchanger has a thermally conductive first plate with a flat first surface for thermal contact with a heat transfer fluid, and a flat second surface for thermal contact with an object to be heated or cooled, such as an electronic component. The first surface is provided with a first surface pattern having a plurality of first grooves, and the second surface is provided with a second surface pattern with a plurality of second grooves. The surface patterns may be configured and applied such that the amount of elongation along the first surface produced by application of the first surface pattern substantially corresponds to or offsets the amount of elongation along the second surface produced by application of the second surface pattern, such that the degree of flatness of the first plate prior to formation of the first and second surface patterns will be preserved, maintained or improved.
Conductive vias in semiconductor packages and methods of forming same
An embodiment package includes a first integrated circuit die encapsulated in a first encapsulant; a first through via extending through the first encapsulant; and a conductive pad disposed in a dielectric layer over the first through via and the first encapsulant. The conductive pad comprises a first region electrically connected to the first through via and having an outer perimeter encircling an outer perimeter of the first through via in a top down view. The package further includes a first dielectric region extending through the first region of the conductive pad. A conductive material of the first region encircles the first dielectric region in the top down view.
ASSEMBLY SUBSTRATES INCLUDING THROUGH HOLE VIAS AND METHODS FOR MAKING SUCH
Various embodiments are related to substrates having one or more well structures with a trapezoidal cylinder shaped through hole via extending from the bottom of the well structure though the substrate.
Bonding method of fixing an object to a rough surface
A bonding method is provided. A sheet structure is placed on a substrate surface, and a surface roughness of a surface of the sheet structure is less than or equal to 1.0 micrometer. A carbon nanotube structure is laid on the surface of the sheet structure. Two ends of the carbon nanotube structure are in direct contact with the substrate surface. An organic solvent is added to the two ends of the carbon nanotube structure. An object is laid on the carbon nanotube structure, and a surface of the object being in direct contact with the carbon nanotube structure has a surface roughness less than or equal to 1.0 micrometer.
Semiconductor arrangement and method for producing a semiconductor arrangement
A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.
BONDING METHOD OF FIXING AN OBJECT TO A ROUGH SURFACE
A bonding method is provided. A sheet structure is placed on a substrate surface, and a surface roughness of a surface of the sheet structure is less than or equal to 1.0 micrometer. A carbon nanotube structure is laid on the surface of the sheet structure. Two ends of the carbon nanotube structure are in direct contact with the substrate surface. An organic solvent is added to the two ends of the carbon nanotube structure. An object is laid on the carbon nanotube structure, and a surface of the object being in direct contact with the carbon nanotube structure has a surface roughness less than or equal to 1.0 micrometer.