A method of liquid assisted binding is provided. The method includes: forming a conductive pad on the substrate; placing a micro device on the conductive pad, such that the micro device is in contact with the conductive pad in which the micro device comprises an electrode facing the conductive pad; forming a liquid layer on the micro device and the substrate after said placing, such that a part of the liquid layer penetrates between the micro device and the conductive pad, and the micro device is gripped by a capillary force produced by said part of the liquid layer; and evaporating the liquid layer such that the electrode is bound to the conductive pad and is in electrical connection with the conductive pad.

A method of restricting a micro device on a conductive pad is provided. The method includes: forming the conductive pad having a first lateral length on a substrate; forming a liquid layer on the conductive pad; and placing the micro device having a second lateral length over the conductive pad such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the conductive pad, the micro device comprising an electrode facing the conductive pad, wherein the first lateral length is less than or equal to twice of the second lateral length.

Described herein methods of manufacturing dual-sided packaged electronic modules that control the distribution of an under-fill material between one or more components and a packaging substrate. The disclosed technologies include under-filling one or more components and deflashing a portion of the under-fill to remove under-fill material prior to attaching solder balls. The deflashing step removes a thin layer of under-fill material that may have coated contact pads for the ball grid array. Because the solder balls are not present during under-fill, there is little capillary action drawing material away from the components being under-filled. This can reduce the frequency of voids under the components being under-filled. Accordingly, the disclosed technologies control under-fill for dual-sided ball grid array packages using under-fill deflash prior to attaching solder balls of the ball grid array.

An electrical joint structure including a substrate, a multi-layer bonding structure, and a blocking layer is provided. The multi-layer bonding structure is present on the substrate and includes a diffusive metal layer and a tin-rich layer. The diffusive metal layer includes a copper-tin alloy on a surface of the diffusive metal layer. The surface faces the substrate. A thickness of the copper-tin alloy is less than or equal to 2 m. The tin-rich layer is present on and in contact with the diffusive metal layer. The blocking layer is present between the multi-layer bonding structure and the substrate and at least in contact with a part of said copper-tin alloy, such that the multi-layer bonding structure is spaced apart from the substrate.

A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.

In one embodiment, methods for making semiconductor devices are disclosed.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

This disclosure is related to post processing steps for integrating of micro devices into system (receiver) substrate or improving the performance of the micro devices after transfer. Post processing steps for additional structure such as reflective layers, fillers, black matrix or other layers may be used to improve the out coupling or confining of the generated LED light. In another example, dielectric and metallic layers may be used to integrate an electro-optical thin film device into the system substrate with the transferred micro devices. In another example, color conversion layers are integrated into the system substrate to create different output from the micro devices.