Provided is a joint structure interposed between a semiconductor element and a substrate, the joint structure including: a Sn phase; Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %; and Ag particles, wherein the Cu alloy particles are each coated with a Cu.sub.6Sn.sub.5 layer, wherein the Ag particles are each coated with a Ag.sub.3Sn layer, wherein the Cu alloy particles and the Ag particles are at least partially bonded to each other through a Cu.sub.10Sn.sub.3 phase, wherein a total of addition amounts of the Cu alloy particles and the Ag particles is 25 mass % or more and less than 65 mass % with respect to the joint structure, and wherein a mass ratio of the addition amount of the Ag particles to the addition amount of the Cu alloy particles is 0.2 or more and less than 1.2.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

A semiconductor device includes a power semiconductor device, a circuit board, and an insulating substrate. The power semiconductor device includes contact pads. Adjacent ones of the contact pads are separated by one of a plurality of gaps. The circuit board includes traces for coupling with the contact pads of the power semiconductor device. The contact pads are physically attached to the traces. The insulating substrate is disposed between the circuit board and the power semiconductor device, where portions of the insulating substrate are disposed in the plurality of gaps, and where the insulating substrate has a monolithic structure.

A semiconductor device includes: a carrier having a die pad and a contact; a semiconductor die having opposing first and second main sides and being attached to the die pad by a first solder joint such that the second main side faces the die pad; and a contact clip having a first contact region and a second contact region. The first contact is attached to the first main side by a second solder joint. The second contact region is attached to the contact by a third solder joint. The first contact region has a convex shape facing towards the first main side such that a distance between the first main side and the first contact region increases from a base of the convex shape towards an edge of the first contact region. The base runs along a line that is substantially perpendicular to a longitudinal axis of the contact clip.

A multi-sided cooling semiconductor package includes a first substrate, a second substrate, semiconductor chips disposed between the first substrate and the second substrate, and first metal preforms. The first substrate includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The second substrate also includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The first metal preforms are disposed between the first substrate and the semiconductor chips and between the second substrate and the semiconductor chips. A first part of the first metal preforms is in direct contact with the upper metal layer of the first substrate, and a second part of the first metal preforms is in direct contact with the lower metal layer of the second substrate.

Provided is a joint structure interposed between a semiconductor element and a substrate, the joint structure including: a Sn phase; Cu alloy particles containing P in an amount of 1 mass % or more and less than 7 mass %; and Ag particles, wherein the Cu alloy particles are each coated with a Cu.sub.6Sn.sub.5 layer, wherein the Ag particles are each coated with a Ag.sub.3Sn layer, wherein the Cu alloy particles and the Ag particles are at least partially bonded to each other through a Cu.sub.10Sn.sub.3 phase, wherein a total of addition amounts of the Cu alloy particles and the Ag particles is 25 mass % or more and less than 65 mass % with respect to the joint structure, and wherein a mass ratio of the addition amount of the Ag particles to the addition amount of the Cu alloy particles is 0.2 or more and less than 1.2.

Provided is a metal paste for joints, containing: metal particles; and linear or branched monovalent aliphatic alcohol having 1 to 20 carbon atoms, in which the metal particles include sub-micro copper particles having a volume average particle diameter of 0.12 μm to 0.8 μM.

Provided is a metal paste for joints, containing: metal particles; and linear or branched monovalent aliphatic alcohol having 1 to 20 carbon atoms, in which the metal particles include sub-micro copper particles having a volume average particle diameter of 0.12 μm to 0.8 μM.

A multi-sided cooling semiconductor package includes a first substrate, a second substrate, semiconductor chips disposed between the first substrate and the second substrate, and first metal preforms. The first substrate includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The second substrate also includes a upper metal layer, a lower metal layer, and a dielectric plate between the upper metal layer and the lower metal layer. The first metal preforms are disposed between the first substrate and the semiconductor chips and between the second substrate and the semiconductor chips. A first part of the first metal preforms is in direct contact with the upper metal layer of the first substrate, and a second part of the first metal preforms is in direct contact with the lower metal layer of the second substrate.

A method of soldering elements together includes providing a substrate having a metal die attach surface, providing a semiconductor die that is configured as a power semiconductor device and having a semiconductor body, a rear side metallization, and a front side layer stack, the front side layer stack having a front side metallization and a contaminant protection layer, arranging the semiconductor die on the substrate with a region of solder material between the die attach surface and the rear side metallization, and performing a soldering process that reflows the region of solder material to form a soldered joint between the metal die attach surface and the rear side metallization, wherein the soldering process comprises applying mechanical pressure to the front side metallization, and wherein the contaminant protection layer is configured to prevent transmission of contaminants into the semiconductor body after the soldering process is completed.