H01L2224/8309

Method of manufacturing semiconductor device, and mounting apparatus
10847434 · 2020-11-24 · ·

A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.

Joint manufacturing method

Provided is a joint manufacturing method including: a step A of preparing a laminate in which two objects to be joined are temporarily adhered with a heat-joining sheet including a pre-sintering layer interposed between the two objects to be joined; a step B of increasing a temperature of the laminate from a temperature equal to or lower than a first temperature defined below to a second temperature; and a step C of holding the temperature of the laminate in a predetermined range after the step B, in which the laminate is pressurized during at least a part of the step B and at least a part of the step C. The first temperature is a temperature at which an organic component contained in the pre-sintering layer is decreased by 10% by weight when the pre-sintering layer is subjected to thermogravimetric measurement.

Method for permanently bonding wafers

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: forming a reservoir in a surface layer on the first contact surface, the first surface layer consisting at least largely of a native oxide material, at least partial filling of the reservoir with a first educt or a first group of educts, the first contact surface making contact with the second contact surface for formation of a prebond connection, forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

ELECTRONIC DEVICE, ELECTRONIC MODULE AND METHODS FOR FABRICATING THE SAME

An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

Electronics package with integrated interconnect structure and method of manufacturing thereof

An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

Electronics package having a multi-thickness conductor layer and method of manufacturing thereof

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

Electronic device, electronic module and methods for fabricating the same

An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.

METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY
20200219848 · 2020-07-09 ·

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

SEMICONDUCTOR DEVICE WITH A LAYERED PROTECTION MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
20200219851 · 2020-07-09 ·

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.

Methods and systems for inhibiting bonding materials from contaminating a semiconductor processing tool

Methods and systems for inhibiting bonding materials from entering a vacuum system of a semiconductor processing tool are disclosed herein. A semiconductor processing tool configured in accordance with a particular embodiment includes a bondhead having a first port, a second port, a first channel fluidly coupled to the first port, and a second channel fluidly coupled to the second port. The first port and first channel together comprise a first opening extending through the bondhead, and the second port and second channel together comprise a second opening extending through the bondhead. The second opening at least partially surrounds the first opening. A first flow unit is coupled to the first port and is configured to withdraw air from the first opening. A second flow unit is coupled to the second port and is configured to provide fluid to or withdraw fluid from the second opening.