A compound and method of use thereof consisting of an A-staged thermoplastic-polyimide (TPI) adhesive, a viscous uncured liquid of polyamic-acid polymer (PAA), the TPI precursor, synthesized and dissolved in a polar aprotic organic solvent, and including, as appropriate, combinations of particulate ceramic and/or metallic thermally conducting, electrically insulating, and thermally conducting, electrically conducting fillers for interface-bonding to create a robust joint between surfaces with conventional lamination processes that utilize relatively moderate temperatures and applied pressures.

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means.

An electronics package includes an insulating substrate, an electrical component having a back surface coupled to a first surface of the insulating substrate, and an insulating structure surrounding at least a portion of a perimeter of the electrical component. A first wiring layer extends from the first surface of the insulating substrate and over a sloped side surface of the insulating structure to electrically couple with at least one contact pad on an active surface of the electrical component. A second wiring layer is formed on a second surface of the insulating substrate and extends through at least one via therein to electrically couple with the first wiring layer.

This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained. Thus, voids and back contamination may be limited to assemble a reliable semiconductor device

Methods and apparatuses for controlled processing of high temperature bonding systems via devices to control heating and cooling systems of a high temperature heating bonding includes use of a sinter fixture device including a plate surface, that is shaped to contact and conform to a contacting surface of a TLPS substrate assembly, and a plurality of channels below the plate surface within a base body of the sinter fixture device shaped to receive heating and cooling elements. A first set of the one or more channels includes a plurality of cross-channels, a cooling medium inlet, and a cooling medium outlet, which cross-channels, cooling medium inlet, and cooling medium outlet are in fluid communication with one another. A second set of the one or more channels includes a plurality of heating element passageways.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 m and less than or equal to 0.8 m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 m and less than or equal to 50 m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300 C., and a content of the solvent having a boiling point of higher than or equal to 300 C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

A semiconductor device includes a semiconductor chip including a substrate and an element region on the substrate, a heat transfer body made of diamond, and a metal layer between the semiconductor chip and the heat transfer body, wherein the substrate includes an amorphous region on a back surface thereof, the amorphous region and the metal layer are bonded to each other, and the metal layer and the heat transfer body are bonded to each other.

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.