The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding.

The semiconductor device having flip chip structure includes: an insulating substrate; a signal wiring electrode disposed on the insulating substrate; a power wiring electrode disposed on the insulating substrate or disposed so as to pass through the insulating substrate; a semiconductor chip disposed in flip chip configuration on the insulating substrate and comprising a semiconductor substrate, a source pad electrode and a gate pad electrode disposed on a surface of the semiconductor substrate, and a drain pad electrode disposed on a back side surface of the semiconductor substrate; agate connector disposed on the gate pad electrode; and a source connector disposed on the source pad electrode. The gate connector, the gate pad electrode and the signal wiring electrode are bonded, and the source connector, the source pad electrode and the power wiring electrode are bonded, by using solid phase diffusion bonding.

The chip bonding apparatus used in a chip bonding method includes a heating unit for heating an anisotropic conductive film at a first temperature; an attachment unit for attaching an integrated circuit chip to the anisotropic conductive film; a stage on which a substrate is seated; a chip transport unit for moving and aligning the integrated circuit chip that is attached to the anisotropic conductive film on the substrate; and a bonding head arranged above the stage to bond the integrated circuit chip that is attached to the anisotropic conductive film onto the substrate through thermo-compression of the integrated circuit chip onto the substrate at a second temperature that is lower than the first temperature.

Provided is a production method for a semiconductor package making it possible to embed, in its irregularities, a thermosetting resin sheet satisfactorily. The method is a production method, for a semiconductor package, including the step of forming a sealed body by pressurizing a stacked body which includes: a chip-temporarily-fixed body comprising a supporting plate, a temporarily-fixing material stacked over the supporting plate, and a semiconductor chip fixed temporarily over the temporarily-fixing material; a thermosetting resin sheet arranged over the chip-temporarily-fixed body; and a separator having a tensile storage elastic modulus of 200 MPa or less at 90 C. and arranged over the thermosetting resin sheet; the sealed body including the semiconductor chip and the thermosetting resin sheet covering the semiconductor chip.

Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.

The present disclosure relates to silver paste, and a preparation method and a use thereof, which belong to the field of device packaging technology. The silver paste of the present disclosure is prepared by a silver-ammonia complex and an aldehyde-containing organic solvent, wherein a molar ratio of the silver-ammonia complex to the aldehyde-containing organic solvent is in a range of from 1:1 to 1:5; the silver-ammonia complex is prepared by a silver -ketocarboxylate and an amino-containing organic solvent; and a molar ratio of the silver -ketocarboxylate to the amino-containing organic solvent is in a range of from 1:1 to 1:5. The silver paste of the present disclosure can achieve large-area (3030 cm.sup.2) packaging and interconnection of a wide-bandgap semiconductor device within 300 C. under a low pressure (1 MPa) or without pressures.

This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained. Thus, voids and back contamination may be limited to assemble a reliable semiconductor device

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained. Thus, voids and back contamination may be limited to assemble a reliable semiconductor device