H01L2224/83102

Semiconductor package and method of manufacturing the same
11694949 · 2023-07-04 · ·

A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

Semiconductor devices and methods of manufacturing semiconductor devices

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

Semiconductor devices and methods of manufacturing semiconductor devices

In one example, a semiconductor device can comprise a unit substrate comprising a unit conductive structure and a unit dielectric structure, and an electronic component coupled to the unit conductive structure. The unit substrate can comprise a portion of a singulated subpanel substrate of a panel substrate. Other examples and related methods are also disclosed herein.

Semiconductor package with chamfered semiconductor device

A semiconductor package includes a semiconductor device, an encapsulating material, and a redistribution structure. The semiconductor device includes a chamfer disposed on one of a plurality of side surfaces of the semiconductor device. The encapsulating material encapsulates the semiconductor device. The redistribution structure is disposed over the encapsulating material and electrically connected to the semiconductor device.

Multi-zone radio frequency transistor amplifiers

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

Multi-zone radio frequency transistor amplifiers

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

Integrated circuit package and method

In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

Integrated circuit package and method

In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

Localized high density substrate routing

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Localized high density substrate routing

Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.