An embodiment device includes: a first dielectric layer; a first photonic die and a second photonic die disposed adjacent a first side of the first dielectric layer; a waveguide optically coupling the first photonic die to the second photonic die, the waveguide being disposed between the first dielectric layer and the first photonic die, and between the first dielectric layer and the second photonic die; a first integrated circuit die and a second integrated circuit die disposed adjacent the first side of the first dielectric layer; conductive features extending through the first dielectric layer and along a second side of the first dielectric layer, the conductive features electrically coupling the first photonic die to the first integrated circuit die, the conductive features electrically coupling the second photonic die to the second integrated circuit die; and a second dielectric layer disposed adjacent the second side of the first dielectric layer.

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

A structure including a substrate having a conductive pad and a connecting structure disposed on the conductive pad and electrically connected to the conductive pad. The connecting structure includes a first metallic layer disposed on the conductive pad, a first intermetallic compound layer disposed on the first metallic layer, a second intermetallic compound layer disposed on the first intermetallic compound layer and a second metallic layer disposed on the second intermetallic compound layer. The first metallic layer comprises copper. The first intermetallic compound layer comprises a first intermetallic compound. The second intermetallic compound layer comprises a second intermetallic compound different from the first intermetallic compound. The second metallic layer comprises tin. The first intermetallic compound contains copper, tin and one of nickel and cobalt.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

A resin interposer having a semiconductor chip mounted thereon to couple the semiconductor chip to a printed circuit board, the resin interposer includes a wiring layer having a front surface to which the semiconductor chip is coupled and formed by alternately laminating an insulating resin and a metal wiring, and a pressure-sensitive adhesive layer formed on a rear surface of the wiring layer and having a through via formed therein to couple the wiring layer and the printed circuit board to each other.

A resin interposer having a semiconductor chip mounted thereon to couple the semiconductor chip to a printed circuit board, the resin interposer includes a wiring layer having a front surface to which the semiconductor chip is coupled and formed by alternately laminating an insulating resin and a metal wiring, and a pressure-sensitive adhesive layer formed on a rear surface of the wiring layer and having a through via formed therein to couple the wiring layer and the printed circuit board to each other.