An electronic device module includes a substrate, a first device and a second device mounted on the substrate, and a shielding frame mounted on the substrate to accommodate the first device. The shielding frame includes a heat dissipating portion stacked on the first device, and posts extended from an edge of the heat dissipating portion and spaced apart from each other. A spacing distance between the posts is smaller than a wavelength of an electromagnetic wave introduced into the first device or output from the first device.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 m in height for direct bonding.

A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.

Systems and methods are provided for producing an integrated circuit package, e.g., an SOIC package, having reduced or eliminated lead delamination caused by epoxy outgassing resulting from the die attach process in which an integrated circuit die is attached to a lead frame by an epoxy. The epoxy outgassing may be reduced by heating the epoxy during or otherwise in association with the die attach process, e.g. using a heating device provided at the die attach unit. Heating the epoxy may achieve additional cross-linking in the epoxy reaction, which may thereby reduce outgassing from the epoxy, which may in turn reduce or eliminate subsequent lead delamination. A heating device located at or near the die attach site may be used to heat the epoxy to a temperature of 55 C.5 C. during or otherwise in association with the die attach process.

A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

Integrated active-matrix multi-color light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. An example integrated device includes a backplane device and different color light emitting diodes (LEDs) devices arranged in different height planar layers on the backplane device. The backplane device includes at least one backplane having a number of pixel circuits. Each LED device includes an array of LEDs each operable to emit light with a particular color and conductively coupled to respective pixel circuits in the backplane to form active-matrix LED sub-pixels. The different color LED sub-pixels form an array of active-matrix multi-color display pixels. Plug vias can be arranged in different planar layers to conductively couple upper-level LEDs to respective pixel circuits in respective regions over the backplane device. The plug vias can extend from an upper planar layer into a lower planar layer to fix the two planar layers together.

A system for packaging integrated circuits includes an integrated circuit having one or more integrated circuit terminals. The system for packaging integrated circuits also includes a substrate having one or more substrate terminals. The system for packaging integrated circuits further includes an electrically conductive adhesive in communication with the integrated circuit terminals and the substrate terminals. The electrically conductive adhesive establishes an electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals. The electrical connection between each of the one or more integrated circuit terminals and the one or more substrate terminals are enclosed in a dielectric. The system for packaging integrated circuits includes a second adhesive in communication with the integrated circuit and the substrate, wherein the second adhesive couples the integrated circuit and substrate together.

This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with unwanted pads and the non-interfering area in the donor substrate is maximized. This enables to transfer the devices to receiver substrate with fewer steps.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 510.sup.6/ C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

An electric module including a first member in which a plurality of first electrodes are arranged on a first face, a second member in which a plurality of second electrodes are arranged on a second face facing the first face, first resin for adhering the first face with the second face, and a bonding portion for electrically connecting each of the first electrodes and each of the second electrodes. The bonding portion is formed of an electroless plating membrane, and the first resin is arranged around the bonding portion.