A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.

A method for bonding a first substrate with a second substrate by means of a connecting layer that is arranged between the substrates and that is comprised of a connecting material with the following steps: applying the connecting material to the first substrate and/or the second substrate in liquid form, and distributing the connecting material between the substrates by bringing the substrates closer and as a result forming the shape of the connecting layer with a thickness t.

An electronic component mounting method including the steps of: providing a first electronic component having a principal surface provided with a plurality of bumps; providing a substrate having a placement area provided with a plurality of first electrodes corresponding to the plurality of bumps; applying flux to the plurality of bumps; applying flux to at least one of the first electrodes adjacent to at least one reinforcement position set on a peripheral portion of the placement area; dispensing a thermosetting resin onto the reinforcement position, and at least partially coating the first electrode adjacent to the reinforcement position, with the thermosetting resin; placing the first electronic component on the substrate such that the bumps land on the corresponding first electrodes, and thus bringing the thermosetting resin into contact with a peripheral edge portion of the first electronic component; and heating the substrate with the first electronic component placed thereon.

A nanowire bonding interconnect for fine-pitch microelectronics is provided. Vertical nanowires created on conductive pads provide a debris-tolerant bonding layer for making direct metal bonds between opposing pads or vias. Nanowires may be grown from a nanoporous medium with a height between 200-1000 nanometers and a height-to-diameter aspect ratio that enables the nanowires to partially collapse against the opposing conductive pads, creating contact pressure for nanowires to direct-bond to opposing pads. Nanowires may have diameters less than 200 nanometers and spacing less than 1 m from each other to enable contact or direct-bonding between pads and vias with diameters under 5 m at very fine pitch. The nanowire bonding interconnects may be used with or without tinning, solders, or adhesives. A nanowire forming technique creates a nanoporous layer on conductive pads, creates nanowires within pores of the nanoporous layer, and removes at least part of the nanoporous layer to reveal a layer of nanowires less than 1 m in height for direct bonding.

A spectroscopic sensor includes a wiring substrate having a main surface, a light detector disposed on the main surface of the wiring substrate, a Fabry-Perot interference filter, a spacer which is provided on the main surface of the wiring substrate and supports the Fabry-Perot interference filter so that the Fabry-Perot interference filter and the light detector are separated from each other, and a stem connected to a ground potential. A second current path which has a smaller electric resistance than that of an arbitrary first current path which extends from the Fabry-Perot interference filter to the light detector via the spacer and the wiring substrate is formed between the Fabry-Perot interference filter and the stem.

An anisotropic conductive film includes a first connection layer and a second connection layer formed on one side of the first connection layer. The first connection layer is obtained by photo-radical polymerization of a photo-radical polymerizable resin layer containing an acrylate compound and a photo-radical polymerization initiator. The second connection layer includes a thermal- or photo-, cationic or anionic polymerizable resin layer containing an epoxy compound and a thermal- or photo-, cationic or anionic polymerization initiator, or a thermal- or photo-radical polymerizable resin layer containing an acrylate compound and a thermal- or photo-radical polymerization initiator. Conductive particles for anisotropic conductive connection are arranged in a single layer on a second connection layer-side surface of the first connection layer.

A semiconductor device includes, an alloy layer sandwiched between a first Ag layer formed on a mounting board or circuit board and a second Ag layer formed on a semiconductor element, wherein the alloy layer contains an intermetallic compound of Ag.sub.3Sn formed by Ag components of the first Ag layer and the second Ag layer and Sn, and wherein a plurality of wires containing Ag are arranged extended from an outside-facing periphery of the alloy layer.

A semiconductor device including: a die paddle having an upper surface; a solder layer disposed on the upper surface of the die paddle; and a die disposed on the solder layer, so that the solder layer is between the die paddle and the die; the solder layer includes a plurality of spacers configured to be, during production of the semiconductor device prior to hardening of the solder layer, movable in relation to the die paddle; and the die paddle includes a plurality of recesses in the upper surface of the die paddle, and the plurality of recesses is configured to receive the plurality of spacers, so that the plurality of spacers is embedded within the plurality of recesses.