Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.

Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.

An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.

In some examples, a system comprises a set of nanoparticles and a set of nanowires extending from the set of nanoparticles.

In one embodiment, a semiconductor device includes a first insulator. The device further includes a first pad provided in the first insulator, and including first and second layers provided on lateral and lower faces of the first insulator in order. The device further includes a second insulator provided on the first insulator. The device further includes a second pad provided on the first pad in the second insulator, and including third and fourth layers provided on lateral and upper faces of the second insulator in order. The device further includes a first portion provided between an upper face of the first pad and a lower face of the second insulator or between a lower face of the second pad and an upper face of the first insulator, and including a metal element same as a metal element included in the first layer or the third layer.

A micro light emitting diode (LED) transfer device includes a transfer part configured to transfer a relay substrate having at least one micro LED; a mask having openings corresponding to a position of the at least one micro LED; a first laser configured to irradiate a first laser light having a first wavelength to the mask; a second laser configured to irradiate a second laser light having a second wavelength different from the first wavelength to the mask; and a processor configured to: control the at least one micro LED to contact a coupling layer of a target substrate, and based on the coupling layer contacting the at least one micro LED, control the first laser to irradiate the first laser light toward the at least one micro LED, and subsequently control the second laser to irradiate the second laser light toward the at least one micro LED.

A micro light emitting diode (LED) transfer device includes a transfer part configured to transfer a relay substrate having at least one micro LED; a mask having openings corresponding to a position of the at least one micro LED; a first laser configured to irradiate a first laser light having a first wavelength to the mask; a second laser configured to irradiate a second laser light having a second wavelength different from the first wavelength to the mask; and a processor configured to: control the at least one micro LED to contact a coupling layer of a target substrate, and based on the coupling layer contacting the at least one micro LED, control the first laser to irradiate the first laser light toward the at least one micro LED, and subsequently control the second laser to irradiate the second laser light toward the at least one micro LED.

The present disclosure relates to a TFT array substrate and a display panel including the same. The TFT array substrate includes a first substrate and a circuit layer disposed on a side of the first substrate; wherein the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer, and a planarization layer; the first electrode layer comprises a plurality of first electrodes disposed on the side of the first substrate, and the first electrodes are electrodes of thin film transistors in the TFT array substrate; the insulating layer is disposed on a side of the first electrode layer away from the first substrate; the first pad layer comprises a plurality of first pads disposed on a side of the insulating layer away from the first electrode layer; the plurality of first pads are electrically connected to the plurality of first electrodes through contact holes respectively penetrating the insulating layer; the planarization layer is disposed on the side of the insulating layer away from the first electrode layer; the insulating layer is provided with a plurality of trenches, and a projection of each of the trenches on the first substrate respectively covers a projection of a corresponding edge of the first pads on the first substrate.

The present disclosure relates to a TFT array substrate and a display panel including the same. The TFT array substrate includes a first substrate and a circuit layer disposed on a side of the first substrate; wherein the circuit layer comprises a first electrode layer, an insulating layer, a first pad layer, and a planarization layer; the first electrode layer comprises a plurality of first electrodes disposed on the side of the first substrate, and the first electrodes are electrodes of thin film transistors in the TFT array substrate; the insulating layer is disposed on a side of the first electrode layer away from the first substrate; the first pad layer comprises a plurality of first pads disposed on a side of the insulating layer away from the first electrode layer; the plurality of first pads are electrically connected to the plurality of first electrodes through contact holes respectively penetrating the insulating layer; the planarization layer is disposed on the side of the insulating layer away from the first electrode layer; the insulating layer is provided with a plurality of trenches, and a projection of each of the trenches on the first substrate respectively covers a projection of a corresponding edge of the first pads on the first substrate.