A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

There is disclosed a packaged semiconductor device comprising: a leadframe having a first thickness; the leadframe comprising a die pad; a semiconductor die thereabove; and epoxy therebetween and arranged to bond the semiconductor die to the die pad; wherein in at least one region under the semiconductor die, the die pad has a second thickness less than the first thickness; wherein the die pad has at least one through-hole in the at least one region; and wherein the epoxy fills the at least one through-hole and extends thereunder and laterally beyond the through-hole. Corresponding leadframes, and an associated method of manufacture are also disclosed.

Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.

A mounting device comprises a substrate stage, a mounting head, an elevating unit, a recognition mechanism, and a control unit. The recognition mechanism acquires position information about a chip recognition mark and a substrate recognition mark using an imaging unit. The control unit calculates an amount of positional deviation between a chip component and a substrate from the position information about the chip recognition mark and the substrate recognition mark, and performs alignment by driving the mounting head and/or the substrate stage according to the amount of the positional deviation. The chip component and the substrate are brought closer with each other and the alignment is performed in a state in which the imaging unit simultaneously images the chip recognition mark and the substrate recognition mark within a depth of field, after which the chip component and the substrate are brought into close contact with each other.

A chip bonding apparatus, includes: a body; a substrate conveyor installed on the body to transfer a substrate; a bonding head conveyor disposed on an upper surface of the body; an alignment unit installed on the body and adjusting a position of the substrate and a position of a chip; and a bonding head installed in the bonding head conveyor and moved and attaching a chip therebelow, wherein the bonding head is provided with a chip bonding unit for attaching the chip in a lower end portion thereof, wherein the chip bonding unit, includes: a chip bonding unit body having an installation groove formed therein; a pushing module having one end portion inserted in the installation groove; and an attachment module having a deformable member deformed by the pushing module; wherein the deformable member is provided with a deformable portion which is deformed by being pressed by the pushing module, and having a bottom surface in contact and exerting a force on the chip to bond the chip to the substrate.

Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

Various embodiments of the teachings herein include a semifinished product for use in the populating of a power electronics component by a connecting method. The product includes an electrically insulating prepreg frame electrically insulated. The prepreg frame is configured for surrounding an applied connecting material at a metallized installation site during the population. A material of the prepreg frame enables simultaneous processability of electrical connection and electrical insulation by compression of the insulation material in the form of the semifinished product since the processing parameters of the electrical connecting material and the semifinished product are compatible.

A collet for compressing an adhesive-attached chip, the collet including a main body having a first pressing surface to which a pressing force from a compressing device is directly transmitted, and a projecting portion projecting from the main body and having a second pressing surface provided along an outer circumference of the first pressing surface, the first pressing surface and the second pressing surface forming a holding surface for holding the adhesive-attached chip.

A light emitting device including a first LED stack, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, and a common electrode electrically connected to a first conductivity type semiconductor layer of each of the first, second, and third LED stacks, in which the common electrode includes a step in at least one of the first, second and third LED stacks.

This invention relates to the process of correcting misalignment and filling voids after a microdevice transfer process. The process involves transfer heads, measurement of offset and misalignment in horizontal, vertical, and rotational errors. An execution of the new offset vector for the next transfer corrects the alignment.