A semiconductor device includes a semiconductor element, a joint material, a heat spreader, and a sealing resin. The semiconductor element includes a main surface. The main surface has a first outer periphery. The sealing resin seals the semiconductor element, the joint material, and the heat spreader. The heat spreader includes a main body and a protrusion. The protrusion is joined to the main surface by the joint material. The main surface has an exposed surface. The exposed surface is located between the first outer periphery and the joint material. The first outer periphery and the exposed surface are exposed from the joint material. The first outer periphery and the exposed surface are sealed with the sealing resin.

A power module for PCB embedding includes: a leadframe; a power semiconductor die with a first load terminal and control terminal at a first side of the die and a second load terminal at the opposite side, the second load terminal soldered to the leadframe; a first metal clip soldered to the first load terminal and forming a first terminal of the power module at a first side of the power module; and a second metal clip soldered to the control terminal and forming a second terminal of the power module at the first side of the power module. The leadframe forms a third terminal of the power module at the first side of the power module, or a third metal clip is soldered to the leadframe and forms the third terminal. The power module terminals are coplanar within +/−30 μm at the first side of the power module.

Provided is a semiconductor device including: a lead frame having an upper surface provided with a concave portion and a lower surface provided with a convex portion; a semiconductor chip fixed to the upper surface of the lead frame; a solder layer provided in the concave portion and fixing the semiconductor chip to the upper surface of the lead frame; and a sealing resin for sealing the semiconductor chip and the lead frame. A thickness of the solder layer is larger than a depth of the concave portion. The sealing resin covers at least a part of the lower surface of the lead frame. At least a part of the convex portion of the lead frame is exposed from the sealing resin.

A semiconductor package includes a semiconductor chip formed with a non-volatile semiconductor memory, a resin encapsulation that encapsulates the semiconductor chip, electrodes in a lattice (solder balls) formed and arrayed in a lattice on a bottom surface of the resin encapsulation. The solder balls include a signal electrode formed within the central region of the array and a dummy electrode formed outside the signal electrode.

A semiconductor device includes a semiconductor element, a sealing member, and a first conductive plate. The semiconductor element includes a first electrode. The sealing member seals the semiconductor element. The first conductive plate includes a first surface facing the first electrode inside the sealing member. The first surface of the first conductive plate includes a mounting region, a roughened region and a non-roughened region. The first electrode is joined to the mounting region. The roughened region is located around the mounting region. The non-roughened region is located between the roughened region and an outer peripheral edge of the first surface. Surface roughness of the roughened region is larger than surface roughness of the non-roughened region.

A temporary fixing composition is provided that is used to temporarily fix a first bonding target material and a second bonding target material to each other before the two bonding target materials are bonded to each other. The temporary fixing composition contains a first organic component having a viscosity of less than 70 mPa.Math.s at 25° C. and a boiling point of 200° C. or lower and a second organic component having a viscosity of 70 mPa.Math.s or greater at 25° C. and a boiling point of 210° C. or higher. It is preferable that, when thermogravimetry-differential thermal analysis is performed under the conditions at a temperature increase rate of 10° C./min in a nitrogen atmosphere with a sample mass of 30 mg, the 95% mass reduction temperature is lower than 300° C.

Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.