A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

The present disclosure is directed to a hybrid conductive ink including: silver nanoparticles and eutectic low melting point alloy particles, wherein a weight ratio of the eutectic low melting point alloy particles and the silver nanoparticles ranges from 1:20 to 1:5. Also provided herein are methods of forming an interconnect including a) depositing a hybrid conductive ink on a conductive element positioned on a substrate, wherein the hybrid conductive ink comprises silver nanoparticles and eutectic low melting point alloy particles, the eutectic low melting point alloy particles and the silver nanoparticles being in a weight ratio from about 1:20 to about 1:5; b) placing an electronic component onto the hybrid conductive ink; c) heating the substrate, conductive element, hybrid conductive ink and electronic component to a temperature sufficient i) to anneal the silver nanoparticles in the hybrid conductive ink and ii) to melt the low melting point eutectic alloy particles, wherein the melted low melting point eutectic alloy flows to occupy spaces between the annealed silver nanoparticles, d) allowing the melted low melting point eutectic alloy of the hybrid conductive ink to harden and fuse to the electronic component and the conductive element, thereby forming an interconnect. Electrical circuits including conductive traces and, optionally, interconnects formed with the hybrid conductive ink are also provided.

A semiconductor device manufacturing method includes a preparation step and a sinter bonding step. In the preparation step, a sinter-bonding work having a multilayer structure including a substrate, semiconductor chips, and sinter-bonding material layers is prepared. The semiconductor chips are disposed on, and will bond to, one side of the substrate. Each sinter-bonding material layer contains sinterable particles and is disposed between each semiconductor chip and the substrate. In the sinter bonding step, a cushioning sheet having a thickness of 5 to 5000 μm and a tensile elastic modulus of 2 to 150 MPa is placed on the sinter-bonding work, the resulting stack is held between a pair of pressing faces, and, in this state, the sinter-bonding work between the pressing faces undergoes a heating process while being pressurized in its lamination direction, to form a sintered layer from each sinter-bonding material layer.

This silver paste is used to form a silver paste layer by applying the silver paste directly on the surface of a copper or copper alloy member, and the silver paste includes a silver powder, a fatty acid silver salt, an aliphatic amine, a high-dielectric-constant alcohol having a dielectric constant of 30 or more, and a solvent having a dielectric constant of less than 30. The content of the high-dielectric-constant alcohol is preferably 0.01% by mass to 5% by mass when an amount of the silver paste is taken as 100% by mass.

A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.

A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.

Joining a second supporting member to one surface of a semiconductor chip through an upper layer joining portion includes: forming, on the one surface, a pre-joining layer by pressure-sintering a first constituent member containing a sintering material on the one surface such that spaces between the plurality of protrusions are filled with the pre-joining layer and the pre-joining layer has a flat surface on a side of the pre-joining layer away from the semiconductor chip; arranging, on the flat surface, the second supporting member through a second constituent member containing a sintering material; and heating and pressurizing the second constituent member. Thereby, an upper layer joining portion is formed by the second constituent member and the pre-joining layer.

Joining a second supporting member to one surface of a semiconductor chip through an upper layer joining portion includes: forming, on the one surface, a pre-joining layer by pressure-sintering a first constituent member containing a sintering material on the one surface such that spaces between the plurality of protrusions are filled with the pre-joining layer and the pre-joining layer has a flat surface on a side of the pre-joining layer away from the semiconductor chip; arranging, on the flat surface, the second supporting member through a second constituent member containing a sintering material; and heating and pressurizing the second constituent member. Thereby, an upper layer joining portion is formed by the second constituent member and the pre-joining layer.

An apparatus having a seal plate which includes rigid hard portions and one or more flexible soft portions located between the hard portions is used for bonding at least one semiconductor device onto a substrate that is supported on a platform. The seal plate is movable between a first position which is spaced from the substrate and a second position whereat a first side of the seal plate is configured to be in contact with the substrate. A diaphragm covers a second side of the seal plate opposite to the first side. A fluid pressure generator exerts a fluid pressure onto the diaphragm to actuate the diaphragm to compress the one or more soft portions to transmit a bonding force onto the at least one semiconductor device during bonding.