A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure laterally surrounding the first conductive structure; and an underfill material, partially surrounding the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the underfill material.

A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure laterally surrounding the first conductive structure; and an underfill material, partially surrounding the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the underfill material.

A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower structure.

An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

An electronic device includes one or more multinode pads having two or more conductive segments spaced from one another on a semiconductor die. A conductive stud bump is selectively formed on portions of the first and second conductive segments to program circuitry of the semiconductor die or to couple a supply circuit to a load circuit. The multinode pad can be coupled to a programming circuit in the semiconductor die to allow programming a programmable circuit of the semiconductor die during packaging. The multinode pad has respective conductive segments coupled to the supply circuit and the load circuit to allow current consumption or other measurements during wafer probe testing in which the first and second conductive segments are separately probed prior to stud bump formation.

A semiconductor device includes: an electrically conductive plate; a semiconductor chip on the electrically conductive plate, the semiconductor chip having a front main electrode on a front surface thereof and a back main electrode on a back surface thereof, the back main electrode being bonded to the electrically conductive plate; and a heat radiating member that is bonded to the front main electrode via a conductive adhesive.

A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

A leadframe includes a die pad having arranged thereon a first semiconductor die with an electrically conductive ribbon extending on the first semiconductor die. The first semiconductor die lies intermediate the leadframe and the electrically conductive ribbon. A second semiconductor die is mounted on the electrically conductive ribbon to provide, on the same die pad, a stacked arrangement of the second semiconductor die and the first semiconductor die with the at least one electrically conductive ribbon intermediate the first semiconductor die and the second semiconductor die. Package size reduction can thus be achieved without appreciably affecting the assembly flow of the device.

An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.