A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

It is an object to provide a highly reliable physical-quantity measurement device which can relax thermal stress at a time of bonding and suppress creep or drift of a sensor output.

To attain the above-described object, a physical-quantity measurement device according to the present invention includes a semiconductor element, and a base board connected to the semiconductor element with a plurality of layers being interposed. In the plurality of layers, a stress relaxing layer including at least metal as a main ingredient and a glass layer including glass as a main ingredient are formed each in a layered form including one or more layers. At least one of the stress relaxing layer and the glass layer includes low-melting-point glass, and a softening point of the low-melting-point glass is equal to or lower than the highest heat temperature that the semiconductor element can resist.

Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

Provided is an imaging device in which the degree of freedom in the layout can be improved. The imaging device includes a first substrate part that includes a sensor pixel to perform photoelectric conversion, and a second substrate part that is disposed on one surface side of the first substrate part and that includes a reading circuit to output a pixel signal based on an electric charge outputted from the sensor pixel. The second substrate part includes a first semiconductor substrate on which a first transistor included in the reading circuit is disposed, and a second semiconductor substrate which is disposed on one surface side of the first semiconductor substrate and on which a second transistor included in the reading circuit is disposed.

A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

A three-dimensional memory device includes field effect transistors located on a substrate, lower metal interconnect structures embedded in first dielectric layers and located over the substrate, a source line located over the first dielectric layers, a stepped dielectric material portion located over the first dielectric layers and including stepped surfaces, an alternating stack of insulating layers and electrically conductive layers located over the source line and contacting the stepped surfaces of the stepped dielectric material portion, and memory stack structures extending through the alternating stack and including a memory film and a vertical semiconductor channel. A lateral extent of the stepped dielectric material portion decreases stepwise with a vertical distance from the substrate, and lateral extents of the electrically conductive layers increase with a vertical distance from the source line.

Provided is an imaging device in which the degree of freedom in the layout can be improved. The imaging device includes a first substrate part that includes a sensor pixel to perform photoelectric conversion, and a second substrate part that is disposed on one surface side of the first substrate part and that includes a reading circuit to output a pixel signal based on an electric charge outputted from the sensor pixel. The second substrate part includes a first semiconductor substrate on which a first transistor included in the reading circuit is disposed, and a second semiconductor substrate which is disposed on one surface side of the first semiconductor substrate and on which a second transistor included in the reading circuit is disposed.

A method of manufacturing a bonded body in which a first body and a second body are bonded using a glass paste. The glass paste includes a crystallized glass frit (A) and a solvent (B). A remelting temperature of the crystallized glass frit (A) is higher than a crystallization temperature thereof which is higher than a glass transition temperature thereof. The method includes: applying the glass paste on at least one of the first and second bodies, bonding the first and second bodies by interposing the glass paste therebetween, heating the bonded first and second bodies to a temperature that is not lower than the crystallization temperature and lower than the remelting temperature of the crystallized glass frit (A), and obtaining the bonded body by cooling the bonded first and second bodies to a temperature that is not higher than the glass transition temperature of the crystallized glass frit.

Provided is a physical quantity measurement device in which a bonding temperature of a bonding layer is lowered to a temperature not affecting an operation of a semiconductor chip and an insulating property of the semiconductor chip and a base is secured. The physical quantity measurement device includes a base (diaphragm), a semiconductor chip (strain detection element) to measure a physical quantity on the basis of stress acting on the base, and a bonding layer to bond the semiconductor chip to the base. The bonding layer has a first bonding layer bonded to the semiconductor chip, a second bonding layer bonded to the base, and an insulating base material disposed between the first bonding layer and the second bonding layer. The first and second bonding layers and contain glass. A thermal expansion coefficient of the first bonding layer is equal to or lower than a thermal expansion coefficient of the second bonding layer, a softening point of the second bonding layer is equal to or lower than a heat resistant temperature of the semiconductor chip, and a softening point of the first bonding layer is equal to or lower than the softening point of the second bonding layer.

A method for integrating heterogeneous elements with elements residing on a target wafer is described. A source die including a compound semiconductor substrate, an etch stop layer and at least one active semiconductor element is provided. The etch stop layer is between the active semiconductor element(s) and the substrate. The etch stop layer is resistant to a plasma etch for the substrate. A bonding agent is provided on a surface of the target wafer. The source die is aligned to and placed on the part of the surface of the target wafer such that the active semiconductor element(s) are between the target wafer's surface and the substrate. The bonding agent is between the source die and the surface of the target wafer. The source die is bonded to the target wafer using the bonding agent. The substrate of the source die is removed, the removal includes performing the plasma etch.