The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10.sup.−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

A semiconductor device in an embodiment includes a first chip on a substrate and a second chip adhered to a first region of the first chip using a first adhesive layer. The second chip is positioned so a second region of the first semiconductor is not overlapped. The first adhesive layer covers a lower surface of the second chip but not the second region. A third chip is adhered to a third region of the second chip with a second adhesive layer. The third chip is positioned so a fourth region of the second chip is not overlapped. The second adhesive layer covers a lower surface of the third chip but not the fourth region. An end of the second adhesive layer is above the second region, but not contacting. A coating covers the fourth region and the ends of the second adhesive layer and third chip.

A semiconductor package includes a metallic pad and leads spaced from the metallic pad by a gap, the metallic pad including a roughened surface. The semiconductor package further includes a semiconductor die including bond pads, and an adhesive between the roughened surface of the metallic pad and the semiconductor die, therein bonding the semiconductor die to the metallic pad, wherein the adhesive includes a resin. The metallic pad further includes a groove surrounding the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic pad.

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

A semiconductor module includes a semiconductor element made of a wide-bandgap semiconductor, the semiconductor element having an upper surface with an edge, a buffer member that covers the edge of the upper surface of the semiconductor element, and a sealing resin that seals the semiconductor element and the buffer member. The buffer member has a thickness equal to or larger than 50 μm.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, amounting layer, switching elements, a moisture-resistant layer and a sealing resin. The substrate has a front surface facing in a thickness direction. The mounting layer is electrically conductive and disposed on the front surface. Each switching element includes an element front surface facing in the same direction in which the front surface faces along the thickness direction, a back surface facing in the opposite direction of the element front surface, and a side surface connected to the element front surface and the back surface. The switching elements are electrically bonded to the mounting layer with their back surfaces facing the front surface. The moisture-resistant layer covers at least one side surface. The sealing resin covers the switching elements and the moisture-resistant layer. The moisture-resistant layer is held in contact with the mounting layer and the side surface so as to be spanned between the mounting layer and the side surface in the thickness direction.

A package structure includes a base material, at least one electronic device, at least one dummy pillar and an encapsulant. The electronic device is electrically connected to the base material. The dummy pillar is disposed on the base material. The encapsulant covers the electronic device and a top end of the dummy pillar.

A semiconductor device and a semiconductor package, the device including a pad interconnection structure that penetrates a first buffer dielectric layer and a second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin, the pad interconnection structure includes a central part, a first intermediate part surrounding the central part; a second intermediate part surrounding the first intermediate part, and an outer part surrounding the second intermediate part, a grain size of the outer part is less than a grain size of the second intermediate part, the grain size of the second intermediate part is less than a grain size of the first intermediate part, and the grain size of the first intermediate part is less than a grain size of the central part.