A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.

A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module.

A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module.

Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate including: forming a lower adhesive layer in a lower part of an insulation film; forming an upper adhesive layer in an upper part of the insulation film to form a base material; forming via holes in the base material; and forming a circuit pattern layer on the upper adhesive layer, so it is effective to improve adhesion power between the molding resin and the insulation film at the time of manufacturing a chip package later.

Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate including: forming a lower adhesive layer in a lower part of an insulation film; forming an upper adhesive layer in an upper part of the insulation film to form a base material; forming via holes in the base material; and forming a circuit pattern layer on the upper adhesive layer, so it is effective to improve adhesion power between the molding resin and the insulation film at the time of manufacturing a chip package later.

A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.

A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.

A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in the direction of thickness of the ceramic substrate so as to form a light exit aperture in a surface of the ceramic substrate, (iii) a second concave section formed within the first concave section in the further direction of thickness of the ceramic substrate so that one or more light-emitting devices are provided therein, (iv) a wiring pattern for supplying electricity, which is provided in the first concave section, and (v) a metalized layer having light-reflectivity, which is (a) provided between the light-emitting device and the surface of the second concave section of the substrate, and (b) electrically insulated from the wiring pattern. On the account of this, the light-emitting apparatus package in which heat is excellently discharged and light is efficiently utilized and a light-emitting apparatus in which the light-emitting apparatus package is used can be obtained.