A semiconductor device includes a semiconductor chip provided inside with a p-n junction, an opaque sealing resin covering a surface of the semiconductor chip, and a functional region arranged between the semiconductor chip and the sealing resin and configured to prevent light, which is generated when a forward current flows through the p-n junction and has a particular wavelength causing deterioration of the sealing resin, from reaching the sealing resin.

A semiconductor device includes: a wiring board, a chip stack provided above the wiring board and including a first semiconductor chip; a second semiconductor chip provided between the wiring board and the first semiconductor chip; a first adhesive layer provided between the first semiconductor chip and the second semiconductor chip and on the second semiconductor chip; and a sealing insulation layer including a first part and a second part, the first part covering the chip stack, and the second part extending between the wiring board and the first semiconductor chip.

A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

A packaged electronic device structure includes a substrate having a major surface. A semiconductor device is connected to the major surface of the substrate, the semiconductor device having a first major surface, a second major surface opposite to the first major surface, and a side surface extending between the first major surface and the second major surface. A package body encapsulates a portion of the semiconductor device, wherein the side surface of the semiconductor device is exposed through a side surface of the package body. In some examples, the side surface of the semiconductor device is an active surface. In some examples, the package body comprises a molded structure that contacts and overlaps the first major surface of the semiconductor device.

A device comprises: a high temperature semiconductor device comprising a first surface, wherein the high temperature semiconductor device comprises an active area and a termination area disposed adjacent to the active area; an inorganic dielectric insulating layer disposed on the first surface, wherein the inorganic dielectric insulating layer fills a volume extending over an entirety of the termination area and comprises a thickness greater than or equal to 25 μm and less than or equal to 500 μm; and an electrical connector connecting the active area of the high temperature semiconductor device to an additional component of the device.

A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip. The stack of second semiconductor chips has a lateral footprint greater than the lateral area of the first portion of the surface of the substrate so that at least a portion of the stack of second semiconductor chips overhangs at least one sidewall of at least one of the spacer and the first semiconductor chip, which extend between the stack of second semiconductor chips and the surface of the substrate.

The present disclosure provides a semiconductor package. The semiconductor package includes a carrier member, a plurality of inductors and a memory chip. The carrier member includes a first surface, a second surface and a centrally-located opening. The carrier member also includes a plurality of conductive pads on the second surface proximal to the opening. The memory chip is attached to the carrier member in a face-down manner. The memory chip includes a plurality of bidirectional and unidirectional signal-transmission pins electrically coupled to the inductors. The memory chip also includes a plurality of bonding pads. A plurality of bonding wires, passing through the opening, electrically connect the bonding pads on the memory chip to the conductive pads on the carrier member. A first insulative structure substantially encapsulates the memory chip and the inductors. A plurality of solder balls are attached to the second surface of the carrier member.

In some embodiments, a sensor package includes: a substrate including a sensing area; a terminal portion disposed on a side of the sensing area of the substrate and including at least one terminal connected to the outside; a first outer wall disposed on the substrate and including a main wall surrounding at least some outer portions of the sensing area; at least one wire patterned and disposed on the substrate and configured to connect the sensing area and the terminal portion to each other; and a cover disposed on the first outer wall to correspond to the sensing area. Part of the main wall is disposed between the sensing area and the terminal portion, and the main wall includes an opening through which the at least one wire passes. Other embodiments may be disclosed and/or claimed.

A sensor package structure is provided and includes a substrate, a sensor chip disposed on the substrate, a padding layer disposed on the substrate, a plurality of wires, a support, and a light-permeable layer disposed on the support. A top side of the padding layer is coplanar with a top surface of the sensor chip, the support is disposed on the top side of the padding layer and the top surface of the sensor chip, and the wires are embedded in the support. Terminals at one end of the wires are connected to the top surface of the sensor chip, and terminals at the other end of the wires are connected to the top side of the padding layer, so that the sensor chip can be electrically coupled to the substrate through the wires and the padding layer.

The semiconductor device includes: an insulating substrate having metal layers provided at a front surface and a back surface; a semiconductor element having a lower surface joined onto the metal layer on a front surface side, and having an electrode on an upper surface; a base plate; a case member; a terminal member; a wiring member that connects the terminal member and the semiconductor element; a metal thin film member that continuously covers a surface of the terminal member and a surface of the electrode connected by the wiring member, and a surface of the wiring member; and a filling member that covers a surface of the metal thin film member and the insulating substrate exposed from the metal thin film member, and is filled in a region surrounded by the base plate and the case member.