A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.

Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first wafer including a first metal structure within a body of the first wafer. The semiconductor structure also includes a second wafer including a second metal structure within a body of the second wafer, where the first wafer is coupled to the second wafer at an interface. The semiconductor structure further includes a metal bonding structure coupled to the first metal structure and the second metal structure and extending through the interface.

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps.

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a second semiconductor structure, a through semiconductor via, and an insulation layer. The first semiconductor structure includes a first circuit layer and a first main bonding layer in the first circuit layer and substantially coplanar with a front face of the first circuit layer. The second semiconductor structure includes a second circuit layer on the first circuit layer and a second main bonding layer in the second circuit layer, and topologically aligned with and contacted to the first main bonding layer. The through semiconductor via is along the second semiconductor structure and the first and second main bonding layer, and extending to the first circuit layer. The insulation layer is positioned on a sidewall of the through semiconductor via.

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.

A method for producing an electronic module includes providing a first substrate including at least one first electrical contacting surface, an electronic component including at least one second electrical contacting surface, and a first material layer made of a thermoplastic material including at least one recess extending through the material layer. The first substrate, the electronic component and the first material layer are arranged with the first material layer disposed between the first substrate and the electronic component, and the at least one first electrical contacting surface, the at least one second electrical contacting surface and the at least one recess aligned relative to one another. The first substrate, the electronic component and the material layer are thermocompression bonded. A joint formed between the at least one first electrical contacting surface and the at least one second electrical contacting surface is surrounded or enclosed by the first material layer.