Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips.

Method and apparatus for assembling a component with a flexible foil, as well as assembled product A method is provided for assembling a component (20) with a flexible foil (10). The method comprising the steps of providing (SI) a flexible foil (10) having a first side (11) with at least one liquid confinement zone (12) and at least one liquid confinement subzone (13) enclosed by the liquid confinement zone, depositing (S2) an alignment liquid (30) in the at least one liquid confinement subzone (13), moving (S3) the component (20) towards the liquid confinement zone, and bringing (S4) a surface (21) of the component facing the flexible foil into contact with the alignment liquid in the at least one liquid confinement subzone and releasing (S5) the component (20). The step of moving (S3) the component (20) towards the flexible foil, and the step of bringing (S4) a surface (21) of the component facing the flexible foil into contact with the alignment liquid, is realized with a gripping tool (130) that includes one or more capillary tubes (131) ending in a downward facing opening (132). At least a portion of the capillary tubes that ends in the downward facing opening (132) is filled with a carrier liquid (135). A first, adhesive force (Fa1) exerted by the carrier liquid on the component is larger than a second force (Fg), that is exerted by gravity on the component and wherein said first adhesive force (Fa1) is smaller than the sum (Fg+Fa2) of said second force (Fg) and a third, adhesive force (Fa2) exerted by the alignment liquid on the component when the component comes into contact with the alignment liquid. The alignment liquid (30) in contact with the component (20) exerts adhesive forces on the component that align the released component with the flexible foil.

Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This off-device approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template may be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

Described herein are methods and systems for forming metal interconnect layers (MILs) on engineered templates and transferring these MILs to device substrates. This off-device approach of forming MILs reduces the complexity and costs of the overall process, allows using semiconductor processes, and reduces the risk of damaging the device substrates. An engineered template is specially configured to release a MIL when the MIL is transferred to a device substrate. In some examples, the engineered template does not include barrier layers and/or adhesion layers. In some examples, the engineered template comprises a conductive portion to assist with selective electroplating. Furthermore, the same engineered template May be reused to form multiple MILs, having the same design. During the transfer, the engineered template and device substrate are stacked together and then separated while the MIL is transitioned from the engineered template to the device substrate.

A display device may include a light emitting element including a first end having a first surface, and a second end having a second surface parallel to the first surface, an organic pattern that overlaps the light emitting element and exposes the first and second surfaces, a first electrode disposed on a substrate and electrically contacting the first end, and a second electrode disposed on the substrate and spaced apart from the first electrode, and electrically contacting the second end. A surface area of the first surface may be less than that of the second surface. A top surface of the organic pattern may be a curved surface.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. A patterned hydrophobic layer defines the locations of the printed dots of the devices. The devices in each group are connected in parallel so that each group acts as a single device. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.

A programmable circuit includes an array of printed groups of microscopic transistors or diodes. The devices are pre-formed and printed as an ink and cured. The devices in each group are connected in parallel so that each group acts as a single device. In one embodiment, about 10 devices are contained in each group so the redundancy makes each group very reliable. Each group has at least one electrical lead that terminates in a patch area on the substrate. An interconnection conductor pattern interconnects at least some of the leads of the groups in the patch area to create logic circuits for a customized application of the generic circuit. The groups may also be interconnected to be logic gates, and the gate leads terminate in the patch area. The interconnection conductor pattern then interconnects the gates for form complex logic circuits.