Patent classifications
H01L2224/95136
DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME AND SUBSTRATE OF THE SAME
A method of manufacturing display device is disclosed. a substrate includes a basal layer and metal contacts on the top surface. An insulation layer is disposed on the top surface and includes a first mounting surface and a bottom surface. Multiple grooves are formed on the insulation layer and each extends from the first mounting surface to the bottom surface. The grooves respectively correspond to the metal contacts and expose respective metal contacts. An electromagnetic force is provided with a direction from the basal layer toward the insulation layer. A droplet containing multiple micro components is provided on the first mounting surface. A configuration of an electrode of the micro component corresponds to a configuration of one of the grooves. The electrode is attracted to the corresponding groove by the electromagnetic force so as to electrically contact the metal contact.
Micro device stabilization post
A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.
LIGHT EMITTING DEVICE AND FLUIDIC MANUFACTURE THEREOF
Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.
BONDED ASSEMBLY CONTAINING LATERALLY BONDED BONDING PADS AND METHODS OF FORMING THE SAME
A bonded assembly includes a first die containing first bonding pads having sidewalls that are laterally bonded to sidewalls of second bonding pads of a second die.
METHOD AND DEVICE FOR BONDING OF CHIPS
A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.
Method for producing curved electronic circuits
A method for producing curved electronic circuits is provided, including placing adhesive elements between electronic chips and curved bearing surfaces, with the chips disposed between the surfaces and a flexible film, and such that the chips, the elements, and the surfaces are arranged in a single volume to be depressurised towards an environment outside the volume, the volume including empty spaces between the chips and the surfaces, the spaces being in fluid communication with each other within the volume; establishing a pressure difference between an inside and an outside of the volume such that the film applies a pressure on and collectively deforms the chips in accordance with the surfaces; and stopping the establishing of the pressure difference, the chips being collectively maintained against the surfaces by the elements such that a shape of each of the chips conforms to a corresponding shape of each of the surfaces.
METHODS AND STRUCTURES FOR DIE-TO-DIE BONDING
Embodiments of die-to-die bonding schemes of three-dimensional (3D) memory devices are provided. In an example, a method for bonding includes dicing one or more device wafers to obtain a plurality of dies, placing at least one first die of the plurality of dies onto a first carrier wafer and at least one second die of the plurality of dies onto a second carrier wafer, and bonding the at least one first die each with a respective second die. The at least one first die and the at least one second die each are functional. In some embodiments, the method also includes removing, respectively, the first carrier wafer and the second carrier wafer to form a plurality of bonded semiconductor devices each having one of the first dies and the respective second die.
LED UNIT, LED DISPLAY AND MANUFACTURING METHOD THEREOF
An LED unit, an LED display and a manufacturing method. The LED unit could include a light emitting body and a weighing element. The weighing element could be arranged on the light emitting body, such that when the LED unit is in assembly fluid, the LED unit could move in a predefined posture and along a predefined direction driven by the weighing element. With the above-mentioned implementation, the present disclosure could facilitate the mass transfer of LED units and enhance production efficiency.
Display device, method of manufacturing the same and substrate of the same
A method of manufacturing display device is disclosed. a substrate includes a basal layer and metal contacts on the top surface. An insulation layer is disposed on the top surface and includes a first mounting surface and a bottom surface. Multiple grooves are formed on the insulation layer and each extends from the first mounting surface to the bottom surface. The grooves respectively correspond to the metal contacts and expose respective metal contacts. An electromagnetic force is provided with a direction from the basal layer toward the insulation layer. A droplet containing multiple micro components is provided on the first mounting surface. A configuration of an electrode of the micro component corresponds to a configuration of one of the grooves. The electrode is attracted to the corresponding groove by the electromagnetic force so as to electrically contact the metal contact.
Wafer-level packaging method and package structure
The present disclosure provides a wafer level packaging method and a package structure. The wafer level packaging method includes: forming a bonding structure including a device wafer and a plurality of first chips bonded to the device wafer; conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips with an insulating layer; conformally covering the insulating layer with a shielding layer; and forming an encapsulation layer on the shielding layer. The wafer level package structure includes: a device wafer; a plurality of first chips bonded to the device wafer; an insulating layer conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips; a shielding layer conformally covering the insulating layer; and an encapsulation layer formed on the shielding layer. The wafer level package structure provides a reduced volume and a reduced thickness.