A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.

A semiconductor package includes a package substrate, a lower semiconductor chip on the package substrate, an interposer on the lower semiconductor chip, the interposer including a plurality of pieces spaced apart from each other, an upper semiconductor chip on the interposer, and a molding member covering the lower semiconductor chip and the interposer.

Method and arrangement for assembling one or more microchips (415; 615; 715; 815; 915; 1015) into one or more holes (422; 722), respectively, in a substrate surface (421; 721) of a separate receiving substrate (420; 720; 820; 1020). The holes (422; 722) of the substrate is for microchip insertion out-of-plane in relation to said substrate surface. Each of said microchips is provided with a ferromagnetic layer (213; 613) of ferromagnetic material. The microchips are placed (503) on said substrate surface (421; 721) and it is applied and moved (504) one or more magnetic fields affecting said ferromagnetic layer (213; 613) of each microchip such that the microchips thereby become out-of-plane oriented in relation to said substrate surface (421; 721) and move over the substrate surface (421; 721) until assembled into said holes (422; 722).

Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. The underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer.

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, an under-fill fillet on side surfaces of the plurality of semiconductor devices, and a molding resin surrounding the plurality of semiconductor devices. An uppermost end of the under-fill fillet includes a planar surface coplanar with an upper surface of a periphery of an uppermost semiconductor device among the plurality of semiconductor devices, and the molding resin completely covers the planar surface.

A semiconductor package includes an interposer, a semiconductor die, an underfill layer and an encapsulant. The semiconductor die is disposed over and electrically connected with the interposer, wherein the semiconductor die has a front surface, a back surface, a first side surface and a second side surface, the back surface is opposite to the front surface, the first side surface and the second side surface are connected with the front surface and the back surface, and the semiconductor die comprises a chamfered corner connected with the back surface, the first side surface and the second side surface, the chamfered corner comprises at least one side surface. The underfill layer is disposed between the front surface of the semiconductor die and the interposer. The encapsulant laterally encapsulates the semiconductor die and the underfill layer, wherein the encapsulant is in contact with the chamfered corner of the semiconductor die.