A package structure including an organic interposer substrate, a semiconductor die, conductive bumps, an underfill, and an insulating encapsulation is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the underfill encapsulates the conductive bumps and is in contact with the chamfered edges of the at least one semiconductor die. The insulating encapsulation covers the organic interposer substrate and laterally encapsulates the least one semiconductor die and the underfill.

A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.

A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness.

A semiconductor device having a semiconductor substrate with first and second main surfaces that face one another in a thickness direction, and a circuit layer disposed on the first main surface. The circuit layer has a first electrode layer on the semiconductor substrate, a dielectric layer on the first electrode layer, a second electrode layer on the dielectric layer, and first and second outer electrodes electrically connected to the first and second electrode layers, respectively. The semiconductor substrate has a first end-portion region in which the circuit layer is not provided on the semiconductor substrate and on the side of the first end surface. In the first end-portion region, a first exposed portion is provided that is exposed between the first main surface and the first end surface.

An electronic device is provided, the electronic device includes a driving substrate (13), the driving substrate includes a plurality of circular grooves and a plurality of rectangular grooves, and a plurality of disc-shaped electronic components, at least one disc-shaped electronic component is disposed in at least one circular groove, an alignment element positioned on a top surface of the at least one disc-shaped electronic component, a diameter of the at least one disc-shaped electronic component is defined as R, a diameter of the alignment element is defined as r, a width of at least one rectangular groove among the rectangular grooves is defined as w, and a height of the at least one rectangular groove is defined as H, and the disc-shaped electronic component and the rectangular groove satisfy the condition of (R+r)/2>(w.sup.2+H.sup.2).sup.1/2.

A semiconductor package includes a buffer, a chip stack mounted on the buffer, an adhesive layer disposed between the buffer and the chip stack, and a molding material surrounding the chip stack. The buffer includes a plurality of trenches disposed adjacent to a plurality of edges of the buffer. Each of the trenches is shorter than a corresponding adjacent edge of a chip area of the buffer.

A semiconductor device transfer structure, a display apparatus, and a method of manufacturing the display apparatus are provided. The semiconductor device transfer structure includes: a substrate; an alignment layer provided on the substrate and including a trap configured to seat a semiconductor device; and a transfer layer provided on the alignment layer and including a groove.

A device transfer substrate includes a plurality of recesses, wherein each of the plurality of recesses includes a first region having a shape of a first figure, a second region having a shape of a second figure, and an overlapping region formed as a portion of the first region partially overlaps a portion of the second region, wherein a maximum width of the overlapping region in a direction intersecting with a straight line passing through a center of the first figure and a center of the second figure is less than a diameter or a diagonal length of the first figure and less than a diameter or a diagonal length of the second figure.

A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 μm. Corresponding methods of producing multi-chip assemblies are also described.