The present disclosure relates to the structure of a micro light-emitting device and an alignment substrate. The light-emitting device according to one embodiment includes an inclined side surface having a three-dimensional shape. The inclined side surface is formed to protrude from one surface of the micro light-emitting device, has magnetism, and includes two different electrodes formed in one direction. In this case, among the two electrodes, one electrode may be formed on a mesa portion, and the other electrode may be formed on the inclined side surface.

A method is provided for fabricating an encapsulated emissive element. Beginning with a growth substrate, a plurality of emissive elements is formed. The growth substrate top surface is conformally coated with an encapsulation material. The encapsulation material may be photoresist, a polymer, a light reflective material, or a light absorbing material. The encapsulant is patterned to form fluidic assembly keys having a profile differing from the emissive element profiles. In one aspect, prior to separating the emissive elements from the handling substrate, a fluidic assembly keel or post is formed on each emissive element bottom surface. In one variation, the emissive elements have a horizontal profile. The fluidic assembly key has horizontal profile differing from the emissive element horizontal profile useful in selectively depositing different types of emissive elements during fluidic assembly. In another aspect, the emissive elements and fluidic assembly keys have differing vertical profiles useful in preventing detrapment.

A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

A cathode configured for a solid-state battery includes a body having grains of inorganic material sintered to one another, wherein the grains comprise lithium. A thickness of the body is from 3 μm to 100 μm. The first major surface and the second major surface have an unpolished granular profile such that the profile includes grains protruding outward from the respective major surface with a height of at least 25 nm and no more than 150 μm relative to recessed portions of the respective major surface at boundaries between the respective grains.

An elastic wave device includes an elastic wave element chip, a bump electrically connected to the elastic wave element chip, a package substrate including an electrode bonded to the bump, the elastic wave element chip mounted on the package substrate with the bump, and a sealing resin portion covering the elastic wave element chip on the package substrate. A space surrounded by the elastic wave element chip, the package substrate, and the sealing resin portion is provided. The elastic wave element chip includes a substrate having piezoelectricity, an interdigital transducer electrode, and a pad electrode. A first main surface of the substrate having piezoelectricity includes a first region and a second region closer to a second main surface than the first region. The interdigital transducer electrode is disposed in the first region. The pad electrode is disposed in the second region and bonded to the bump.

A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

Packaged devices are provided for use inside an electronic system that provides access for molding compound or cables by using groove-like features on the bottom of a device package or on top of a substrate, and methods regarding the same. The groove-like features prevent voids in the encapsulant before and after packaging of the electronic system.

A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion. The first insulating encapsulation laterally encapsulates the second semiconductor die, the first conductive pillars and the second portion.

A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall.