A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

A semiconductor structure includes a first semiconductor die containing a recesses, and a second semiconductor die which is embedded in the recess in the first semiconductor die and is bonded to the first semiconductor die.

Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

Disclosed is a silicon photonics-based electronic-photonic integrated circuit (EPIC). The silicon photonics-based EPIC includes a silicon photonic integrated circuit (PIC) chip in which an optical device is mounted on a silicon-on-insulator (SOI) wafer including a trench region, an electronic integrated circuit (EIC) chip mounted in the trench region of the PIC chip, and an electrical interface configured to connect an electrode pad of the PIC chip and an electrode pad of the EIC chip.

The purpose of the present invention is to provide an electronic circuit connection method and an electronic circuit capable of improving the reliability of electrical connection. A connection method for an electronic circuit 100 includes: a process of forming a first metal bumps 30 and a second metal bump 40, each of which has a cone shape; and a process of joining a first electrode pad 12 and a third electrode pad 22 by the first metal bump 30 and joining a second electrode pad 13 and a fourth electrode pad 23 by the second metal bump 40, wherein at least one region of between a first region 11a and a second region 11b in a first connection surface 11 and between a third region 21a and a fourth region 21b in a second connection surface 21 has a step 11c, and the first metal bump 30 and the second metal bump 40 have different heights so as to correct a height H1 of the step 11c.

A system and method. The system may include an integrated circuit (IC) die. The IC die may have two faces and sides. The system may further include mold material. The mold material may surround at least the sides of the IC die. The IC die may be mechanically interlocked with the mold material.

A system and method. The system may include an integrated circuit (IC) die having two faces and sides. The system may further include mold material surrounding at least the sides of the IC die. The system may further include a redistribution layer and signal pads. The redistribution layer may be positioned between (a) the signal pads and (b) the mold material and the IC die. The redistribution layer may have conductive paths at least connecting the IC die and at least some of the signal pads. A a surface of the mold material may abut the redistribution layer. The surface of the mold material may include at least one recessed area having at least one conductive feature connected to at least one of the conductive paths or the IC die.

A semiconductor device has a semiconductor die with a sensor and a cavity formed into a first surface of the semiconductor die to provide access to the sensor. A protective layer is formed on the first surface of the semiconductor die around the cavity. An encapsulant is deposited around the semiconductor die. The protective layer blocks the encapsulant from entering the cavity. With the cavity clear of encapsulant, liquid or gas has unobstructed entry into cavity during operation of the semiconductor die. The clear entry for the cavity provides reliable sensor detection and measurement. The semiconductor die is disposed over a leadframe. The semiconductor die has a sensor. The protective layer can be a film. The protective layer can have a beveled surface. A surface of the leadframe can be exposed from the encapsulant. A second surface of the semiconductor die can be exposed from the encapsulant.

A semiconductor die is proposed, wherein the semiconductor die comprises a microelectronic section and a sensor section. The microelectronic section comprises an integrated circuit. The sensor section adjoins an edge of the semiconductor die. A sensor is also proposed, which comprises such a semiconductor die.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.