The disclosure provides a printed circuit board structure. The printed circuit board structure includes a printed circuit board, a semiconductor chip, a first pad, a second pad, a conductive wire, and a third pad. The semiconductor chip is disposed on the printed circuit board. The first pad is disposed on the semiconductor chip. The second pad is disposed on the printed circuit board. The conductive wire electrically connects the first pad and the second pad. The third pad is disposed between the first pad and the second pad. The conductive wire has a portion located on the third pad.

Techniques are disclosed for forming a frame on the backplane comprising structures at least partially circumscribing or enclosing metal contacts on the backplane. In some embodiments, the frame may comprise a photoresist. The dimensions and structural integrity of the frame can help prevent misalignment and/or damage of physical obtrusions of light-emitting structures during a bonding process of the light-emitting structures to the backplane.

Provided is a highly reliable semiconductor device capable of reducing stress generated in a semiconductor element even when a highly elastic joining material such as a Pb-free material is used in a power semiconductor having a double-sided mounting structure. The semiconductor device includes a semiconductor element including a gate electrode only on one surface, an upper electrode connected to the surface of the semiconductor element on which the gate electrode is provided, and a lower electrode connected to a surface opposite to the surface of the semiconductor element on which the gate electrode is provided. A connection end portion of the upper electrode with the surface of the semiconductor element on which the gate electrode is provided is located inside an end portion of the surface of the semiconductor element on which the gate electrode is provided, and a connection end portion of the lower electrode with the opposite surface of the semiconductor element is located inside an end portion of the opposite surface of the semiconductor element.

A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

A method includes disposing a patterned conductor layer directly on mold material in a fan-out space adjacent to an integrated circuit (IC) chip in a reconstituted wafer. The patterned conductor layer is limited or confined in spatial extent to the fan-out space. The method further includes configuring the patterned conductor layer disposed directly on mold material as a first redistribution layer (RDL) in a fan-out package of the IC chip to carry signals associated with at least one input-output (I/O) contact on the chip.

Memory devices, memory systems, and systems, include memory devices with a bonding pad region for coupling command-and-address (CA) input signals and a memory cell region for storing information in memory cells. A centralized CA interface region includes input circuits coupled to the CA input signals. At least two of the input circuits are configured in pairs. Each pair includes a first input circuit coupled to a first input and configured to generate a first output and a second input circuit coupled to a second input and configured to generate a second output. Each pair also includes a swap circuit disposed between the first input circuit and the second input circuit. The swap circuit selects one of the first output or the second output for a first internal signal and selects the other of the first output and the second output for a second internal signal responsive to a control signal.

A semiconductor device, including a semiconductor chip having a first main electrode on a front surface thereof, the first main electrode having a plurality of bonded regions, and a plurality of wires that are bonded respectively to the plurality of bonded regions of the first main electrode. In a top view of the semiconductor device, the plurality of bonded regions do not overlap in either a predetermined first direction, or a second direction perpendicular to the predetermined first direction.

A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.

A light-emitting device includes: a package defining a recess; a light-emitting element mounted on surface that defines a bottom of the recess; and a sealing member disposed in the recess so as to cover the light-emitting element and made of a light-transmissive resin that contains a filler with an average particle diameter of 200 nm or more and 500 nm or less. The sealing member comprises a filler-containing layer, which contains the filler, and a light-transmissive layer that are layered in an order from a bottom side of the recess. The filler-containing layer has a thickness of equal to or larger than a height of the light-emitting element.