The present disclosure provides a semiconductor device. The semiconductor device includes a first chip and a second chip. The second chip is bonded over and electrically connected to the first chip. The second chip includes a seal ring disposed at a periphery of the second chip and within the second chip. From a top view, the second chip includes a first number of sides and the seal ring includes a second number of sides. The first number is greater than four, and the second number is equal to or greater than the first number.

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

In some examples, a device comprises a substrate including a notch formed in a surface of the substrate and a semiconductor die positioned in the notch and including an electrochemical sensor on an active surface of the semiconductor die. The device also comprises a chemically inert member abutting the surface of the substrate and including an orifice in vertical alignment with the electrochemical sensor as a result of the semiconductor die being positioned in the notch. The device also comprises a compressed o-ring seal positioned between the chemically inert member and the active surface of the semiconductor die, the compressed o-ring seal circumscribing the electrochemical sensor.

Memory devices are disclosed. A memory device may include a bonding pad region for coupling command-and-address (CA) input signals and a memory cell region for storing information in memory cells. The memory device may also include a centralized CA interface region including input circuits coupled to the CA input signals. At least two of the input circuits are configured in pairs. Each pair includes a swap circuit configured to select one of a first CA output and a second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal responsive to a control signal. Memory systems and systems are also disclosed.

An electronic device includes a wiring board and a semiconductor device on the wiring board's main surface. The semiconductor device includes a semiconductor chip on a die pad sealed by a sealing body. A back surface of the die pad is directed to a main surface of the sealing body. A back surface of the sealing body faces the main surface of the wiring board. First and second electrodes are formed on the wiring board and in the sealing body, respectively. The second electrode is disposed in the back surface of the sealing body, and is bonded to a metal plate connecting a lead and a pad. A distance between the first and second electrodes is shorter than that between the metal plate and the first electrode. The first and second electrodes overlap each other in a plan view. A capacitor is composed of the first and second electrodes.

To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged.

A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

An integrated circuit IC package with one or more pins protruding from the IC package for electrically connecting the IC package with a printed circuit board PCB is presented. The IC package has a first die with a first electronic component, a second die with a second electronic component, and a conductive plate having a plane surface. The first electronic component may be a semiconductor power device and the second electronic component may be a control circuit. The plane surface of the conductive plate is electrically connected to both a plane surface of the first die and one or more pins such that an electrical connection is established between the first die and the one or more pins. The second die may be arranged on top of the conductive plate. Alternatively, a third die with a third electronic component may be arranged on top of the conductive plate.

Provided are a paste material, a method of forming the paste material, a wiring member formed from the paste material, and an electronic device including the wiring member. The paste material may include a plurality of liquid metal particles and a polymer binder. The paste material may further include a plurality of nanofillers. At least some of the plurality of nanofillers may each have an aspect ratio equal to or greater than about 3. A content of the plurality of liquid metal particles may be greater than a content of the polymer binder and may be greater than a content of the plurality of nanofillers. The wiring member may be formed by using the paste material, and the wiring member may be used in various electronic devices.

Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag, or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.