Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device includes a semiconductor chip having a passivation film, a stress relieving layer provided on the passivation film, and a groove formed in a periphery of a surface of the semiconductor chip, the groove being provided inside of an edge of the semiconductor chip, wherein the stress relieving layer is partly disposed in the groove.

Claims

1. A semiconductor device comprising: a semiconductor chip having a passivation film; a stress relieving layer provided over the passivation film for absorbing and relieving an externally applied stress; and a sealing resin layer provided on the stress relieving layer for sealing a front side of the semiconductor chip, wherein: the semiconductor chip has a groove formed therein from a front surface thereof at a peripheral edge portion of the front surface, in a sectional view of the semiconductor device perpendicular to the groove, a portion of the front surface separates the groove from one side surface of the semiconductor device that is closer to the groove than another side surface of the semiconductor device, the portion of the front surface has a first portion and a second portion facing the first portion across the groove, and the sealing resin layer has a side surface which is substantially flush with a side surface of the stress relieving layer.

2. A semiconductor device comprising: a semiconductor chip having a passivation film; a stress relieving layer provided over the passivation film for absorbing and relieving an externally applied stress; and an interlayer film provided between the passivation film and a semiconductor substrate serving as a base of the semiconductor chip, wherein: the semiconductor chip has a groove formed therein from a front surface thereof at a peripheral edge portion of the front surface, in a sectional view of the semiconductor device perpendicular to the groove, a portion of the front surface separates the groove from one side surface of the semiconductor device that is closer to the groove than another side surface of the semiconductor device, the portion of the front surface has a first portion and a second portion facing the first portion across the groove, the stress relieving layer is partly disposed in the groove, and the stress relieving layer extends to side surfaces of the passivation film and the interlayer film to cover the side surfaces of the passivation film and the interlayer film.

3. A semiconductor device comprising: a semiconductor chip having a passivation film; a sealing resin layer provided over the passivation film for sealing a front surface of the semiconductor chip; and a stress relieving layer provided between the passivation film and the sealing resin layer for absorbing and relieving an externally applied stress, wherein: the sealing resin layer extends to a side surface of the passivation film to cover the side surface, the semiconductor chip has a groove formed therein from the front surface thereof at a peripheral edge portion of the front surface, in a sectional view of the semiconductor device perpendicular to the groove, a portion of the front surface separates the groove from one side surface of the semiconductor device that is closer to the groove than another side surface of the semiconductor device, and the stress relieving layer is substantially flush with the side surface of the passivation film.

4. The semiconductor device according to claim 3, wherein the sealing resin layer is partly disposed in the groove.

5. The semiconductor device according to claim 4, wherein the passivation film is divided into a center portion and a peripheral portion disposed on opposite sides of the groove, the center portion completely covering a device formation region of the semiconductor chip, the peripheral portion being spaced a predetermined distance from a periphery of the center portion and surrounding the center portion.

6. The semiconductor device according to claim 4, further comprising a stress relieving layer provided between the passivation film and the sealing resin layer for absorbing and relieving an externally applied stress, wherein: the stress relieving layer is partly disposed in the groove.

7. The semiconductor device according to claim 6, wherein the sealing resin layer extends to a side surface of the stress relieving layer.

8. The semiconductor device according to claim 4, wherein: the groove is provided along an outermost peripheral edge of the front surface of the semiconductor chip, and the groove has a width which is greater than 5 m as measured within a plane containing the front surface of the semiconductor chip, and a depth which is greater than 3 m and smaller than 50 m as measured perpendicularly to the plane.

9. The semiconductor device according to claim 8, wherein the groove has a triangular sectional shape which is tapered toward a rear surface of the semiconductor chip.

10. The semiconductor device according to claim 3, wherein the sealing resin layer extends to a side surface of the stress relieving layer.

11. A semiconductor device comprising: a semiconductor chip having a passivation film; a sealing resin layer provided over the passivation film for sealing a front surface of the semiconductor chip; and an interlayer film provided between the passivation film and a semiconductor substrate serving as a base of the semiconductor chip, wherein: the sealing resin layer extends to a side surface of the passivation film to cover the side surface, the semiconductor chip has a groove formed therein from the front surface thereof at a peripheral edge portion of the front surface, in a sectional view of the semiconductor device perpendicular to the groove, a portion of the front surface separates the groove from one side surface of the semiconductor device that is closer to the groove than another side surface of the semiconductor device, the sealing resin layer is partly disposed in the groove, and the sealing resin layer extends to side surfaces of the passivation film and the interlayer film to cover the side surfaces of the passivation film and the interlayer film.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a sectional view illustrating the construction of a semiconductor device according to a first embodiment of the present invention.

(2) FIGS. 2A-2D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 1.

(3) FIG. 3 is a sectional view illustrating the construction of a semiconductor device according to a second embodiment of the present invention.

(4) FIGS. 4A-4D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 3.

(5) FIG. 5 is a sectional view for explaining the construction of a semiconductor device according to a third embodiment of the present invention.

(6) FIG. 6 is a sectional view for explaining the construction of a semiconductor device according to a fourth embodiment of the present invention.

(7) FIGS. 7A-7D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 6.

(8) FIG. 8 is a sectional view for explaining the construction of a semiconductor device according to a fifth embodiment of the present invention.

(9) FIG. 9 is a sectional view for explaining the construction of a semiconductor device according to a sixth embodiment of the present invention.

(10) FIG. 10 is a sectional view illustrating the construction of a semiconductor device according to a seventh embodiment of the present invention.

(11) FIGS. 11A-11D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 10.

(12) FIG. 12 is a sectional view illustrating the construction of a semiconductor device according to an eighth embodiment of the present invention.

(13) FIGS. 13A-13D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 12.

(14) FIG. 14 is a sectional view illustrating a modification of the construction shown in FIG. 10, in which a groove is formed as having a depth equivalent to the thickness of the passivation film.

(15) FIG. 15 is a sectional view illustrating an arrangement in which the seventh embodiment is applied to a semiconductor device having a multilevel interconnection structure.

(16) FIG. 16 is a sectional view illustrating the construction of a semiconductor device according to a ninth embodiment of the present invention.

(17) FIG. 17 is an enlarged view for explaining the dimensions of a groove of the semiconductor device shown in FIG. 16.

(18) FIGS. 18A-18D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 16.

(19) FIG. 19 is a sectional view illustrating the construction of a prior art semiconductor device.

BEST MODE FOR CARRYING OUT THE INVENTION

(20) Embodiments of the present invention will hereinafter be described in detail with reference to the attached drawings.

(21) FIG. 1 is a sectional view illustrating the construction of a semiconductor device according to a first embodiment of the present invention. The semiconductor device is a semiconductor device employing the WL-CSP technique, and includes a semiconductor chip 1, a passivation film (surface protection film) 11 covering a front surface of the semiconductor chip 1 (on a side formed with a functional device), a stress relieving layer 2 provided on the passivation film 11, rewirings 3 provided on the stress relieving layer 2, a sealing resin layer 4 provided over the rewirings 3, and metal balls 5 provided on the sealing resin layer 4.

(22) The semiconductor chip 1 is of a rectangular shape as seen in plan, and has a groove 12 formed in a peripheral edge portion of the outermost front surface thereof. The formation of the groove 12 is achieved by cutting away a peripheral edge portion of the outermost front surface of the semiconductor chip 1 having, for example, a square sectional shape having a width of 10 to 20 m and a depth of 10 to 100 m.

(23) The passivation film 11 is composed of silicon oxide or silicon nitride, and covers the entire front surface of the semiconductor chip 1 except the groove 12. The passivation film 11 has pad openings 113 through which parts of an internal interconnection of a metal such as aluminum provided in the front surface of the semiconductor chip 1 are exposed as electrode pads 6.

(24) The stress relieving layer 2 is composed of, for example, polyimide, and is adapted to absorb and relieve a stress applied to the semiconductor device. The stress relieving layer 2 has a rectangular shape which is slightly smaller than the passivation film 11 as seen in plan. Further, the stress relieving layer 2 has through-holes 21 provided at positions opposed to the respective electrode pads 6 as extending therethrough.

(25) The rewirings 3 are composed of a metal material such as copper, and provided on a surface of the stress relieving layer 2 as extending to positions opposed to the respective metal balls 5 with the intervention of the sealing resin layer 4.

(26) The sealing resin layer 4 is composed of, for example, an epoxy resin, and seals the front side of the semiconductor chip 1. The sealing resin layer 4 completely covers front surfaces of the passivation film 11, the stress relieving layer 2 and the rewirings 3, and extends from the front surfaces to side surfaces of these layers to completely fill the groove 12 of the semiconductor chip 1. The sealing resin layer 4 has a flat front surface, and side surfaces flush with side surfaces of the semiconductor chip 1. Thus, the semiconductor device has a generally rectangular solid shape which has a size equivalent to the size of the semiconductor chip 1 as seen in plan.

(27) Flat cylindrical posts 7 of a metal such as copper are respectively provided between the rewirings 3 and the metal balls 5 as extending through the sealing resin layer 4. The rewirings 3 are respectively connected to the metal balls 5 via the posts 7.

(28) The metal balls 5 serve as external connection terminals for connection (external connection) to a wiring board not shown, and are formed of a metal material such as solder as having a ball-like shape.

(29) With the aforesaid arrangement, the side surfaces of the passivation film 11 are covered with the sealing resin layer 4, and are not exposed to the side surfaces of the semiconductor device. Therefore, separation and cracking of the passivation film 11 is prevented, which may otherwise occur due to a stress applied to a side surface of the semiconductor device.

(30) Further, the groove 12 is provided in the peripheral edge portion of the outermost front surface of the semiconductor chip 1, and the sealing resin layer 4 is partly disposed in the groove 12. Therefore, a portion of the sealing resin layer 4 disposed in the groove 12 also absorbs the stress applied to the side surface of the semiconductor device, so that the separation and cracking of the passivation film 11 can be more assuredly prevented.

(31) FIGS. 2A-2D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 1. First, a wafer W formed with a plurality of semiconductor chips 1 and having a front surface entirely covered with a passivation film 11 is prepared. As shown in FIG. 2A, pad openings 113 are formed in the passivation film 11 for exposing electrode pads 6, and then stress relieving layers 2 and rewirings 3 are formed in this order on the passivation film 11.

(32) The stress relieving layers 2 are not present on dicing lines L defined between the semiconductor chips 1. Therefore, the stress relieving layers 2 disposed on adjacent ones of the semiconductor chips 1 on opposite sides of each of the dicing lines L are spaced a predetermined distance from each other, so that the passivation film 11 is partly exposed along the dicing line L between the stress relieving layers 2.

(33) In turn, as shown in FIG. 2B, a recess 120 is formed along the dicing line L as extending from the front surface of the passivation film 11 to below the passivation film 11. The formation of the recess 120 is achieved, for example, by a half-cutting process for half-cutting the resulting wafer from the front side of the passivation film 11 with the use of a blade (not shown) which has a greater thickness (width) than a dicing blade to be used for dicing the wafer W to separate the semiconductor chips 1 from each other, or by a laser machining process. Where the blade is used, the width and the depth of the recess 120 (groove 12) are controlled by the thickness of the blade and a cut amount.

(34) Thereafter, as shown in FIG. 2C, a sealing resin layer 4 is formed over the entire front surface of the resulting wafer W. The formation of the sealing resin layer 4 is achieved by applying an uncured epoxy resin over the entire front surface of the wafer W and curing the applied epoxy resin. After posts 7 are formed at predetermined positions in the sealing resin layer 4, metal balls 5 are formed on the respective posts 7. The formation of the posts 7 is achieved by forming through-holes in the sealing resin layer 4 and supplying a metal material into the through-holes to fill the through-holes by electroplating.

(35) Then, as shown in FIG. 2D, the resulting wafer W is cut (diced) together with the sealing resin layer 4 along the dicing lines L with the use of the dicing blade not shown. Thus, the semiconductor device shown in FIG. 1 is provided.

(36) FIG. 3 is a sectional view illustrating the construction of a semiconductor device according to a second embodiment of the present invention. In FIG. 3, components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1.

(37) In the semiconductor device shown in FIG. 3, the semiconductor chip 1 is formed with no groove 12, and the side surfaces of the passivation film 11 are flush with the side surfaces of the stress relieving layer 2.

(38) In a production process for the semiconductor device having such a construction, as shown in FIG. 4A, for example, a wafer W covered with a passivation film 11 is prepared, and stress relieving layers 2 and rewirings 3 are formed in this order on the passivation film 11. Thereafter, as shown in FIG. 4B, a portion of the passivation film 11 exposed between the stress relieving layers 2 is etched away by using the stress relieving layers 2 as a mask. That is, a portion of the passivation film 11 present in a zone defined along each of dicing lines L and having a predetermined width is exposed between the stress relieving layers 2 disposed on adjacent ones of the semiconductor chips 1 on opposite sides of the dicing line L. The portion of the passivation film 11 on the dicing line L is removed by etching with the use of the stress relieving layers 2 as the mask.

(39) The etching of the passivation film 11 with the use of the stress relieving layers 2 as the mask is achieved by using an etching liquid which is capable of dissolving the passivation film 11 but incapable of dissolving the stress relieving layers 2. Where the passivation film 11 is composed of silicon oxide, for example, the etching of the passivation film 11 with the use of the stress relieving layers 2 as the mask may be achieved by using nitric acid as the etching liquid. The etching is not limited to the wet etching, but dry etching such as RIE (reactive ion etching) may be employed for the removal of the portion of the passivation film 11 exposed between the stress relieving layers 2.

(40) After the etching of the passivation film 11, as shown in FIG. 4C, a sealing resin layer 4 is formed over the entire front surface of the resulting wafer W, and posts 7 and metal balls 5 are formed. Then, as shown in FIG. 4D, the resulting wafer W is cut (diced) together with the sealing resin layer 4 along the dicing lines L with the use of a dicing blade not shown, whereby the semiconductor device shown in FIG. 3 is provided.

(41) FIG. 5 is a sectional view for explaining the construction of a semiconductor device according to a third embodiment of the present invention. In FIG. 5, components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1.

(42) In the semiconductor device shown in FIG. 5, the semiconductor chip 1 includes an interlayer film 9 such as of silicon oxide or silicon nitride provided between the electrode pads 6 (internal interconnection) formed in the front surface of the semiconductor chip 1 and a semiconductor substrate serving as a base of the semiconductor chip 1. The groove 12 extends to below the interlayer film 9 (into the semiconductor substrate), and the sealing resin layer 4 is partly disposed in the groove 12, whereby the side surfaces of the passivation film 11 and the interlayer film 9 are covered with the sealing resin layer 4.

(43) With this arrangement, separation and cracking of the passivation film 11 and the interlayer film 9 can be prevented, which may otherwise occur due to a stress applied to a side surface of the semiconductor device.

(44) FIG. 6 is a sectional view for explaining the construction of a semiconductor device according to a fourth embodiment of the present invention. In FIG. 6, components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1.

(45) In the semiconductor device shown in FIG. 6, the stress relieving layer 2 provided on the passivation film 11 extends from the front surface to the side surfaces of the passivation film 11 to completely fill the groove 12 formed in the peripheral edge portion of the front surface of the semiconductor chip 1. The sealing resin layer 4 completely covers the front surface of the stress relieving layer 2.

(46) With this arrangement, the side surfaces of the passivation film 11 are covered with the stress relieving layer 2 and, therefore, are not exposed to side surfaces of the semiconductor device. Hence, separation and cracking of the passivation film 11 can be prevented, which may otherwise occur due to a stress applied to the side surface of the semiconductor device.

(47) In addition, the groove 12 is provided in the peripheral edge portion of the outermost front surface of the semiconductor chip 1, and the stress relieving layer 2 is partly disposed in the groove 12. Therefore, a portion of the stress relieving layer 2 disposed in the groove 12 also absorbs the stress applied to the side surface of the semiconductor device, thereby more assuredly preventing the separation and cracking of the passivation film 11.

(48) FIGS. 7A-7D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 6. In the production process for the semiconductor device shown in FIG. 6, a wafer W formed with a plurality of semiconductor chips 1 and having a front surface entirely covered with a passivation film 11 is first prepared. In turn, as shown in FIG. 7A, pad openings 113 are formed in the passivation film 11 for exposing electrode pads 6, and then a recess 120 having a predetermined width is formed along each of dicing lines L as extending from a surface of the passivation film 11 to below the passivation film 11.

(49) After the formation of the recess 120, as shown in FIG. 7B, stress relieving layers 2 each having through-holes 21 are formed on the passivation film 11. The stress relieving layers 2 are not present in a portion having a smaller width than the recess 120 on the dicing line L defined between the semiconductor chips 1. Therefore, the stress relieving layers 2 disposed on adjacent ones of the semiconductor chips 1 on opposite sides of the dicing line L are spaced from each other, so that the semiconductor chips 1 (wafer W) are partly exposed on the dicing line L between the stress relieving layers 2.

(50) In turn, as shown in FIG. 7C, rewirings 3 and a sealing resin layer 4 are formed, and then posts 7 are formed at predetermined positions in the sealing resin layer 4. Further, metal balls 5 are formed on the respective posts 7.

(51) Then, as shown in FIG. 7D, the resulting wafer W is cut (diced) together with the sealing resin layer 4 along the dicing lines L with the use of a dicing blade (not shown) having a thickness (width) substantially equivalent to the width of the portion of the recess 120 free from the stress relieving layers 2. Thus, the semiconductor device shown in FIG. 6 is provided.

(52) FIG. 8 is a sectional view for explaining the construction of a semiconductor device according to a fifth embodiment of the present invention. In FIG. 8, components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1.

(53) In the semiconductor device shown in FIG. 8, the stress relieving layer 2 provided on the passivation film 11 extends from the front surface to the side surfaces of the passivation film 11, and is partly disposed in the groove 12 formed in the peripheral edge portion of the outermost front surface of the semiconductor chip 1. Further, the sealing resin layer 4 provided over the stress relieving layer 2 extends from the front surface to the side surfaces of the stress relieving layer 2 to cover the front surface and side surfaces of the passivation film 11 from the outside of the stress relieving layer 2. The groove 12 formed in the peripheral edge portion of the outermost front surface of the semiconductor chip 1 is completely filled with the stress relieving layer 2 and the sealing resin layer 4.

(54) With this arrangement, the side surfaces of the passivation film 11 are covered with the stress relieving layer 2, and the stress relieving layer 2 is covered with the sealing resin layer 4 from the outside thereof. Therefore, the separation and cracking of the passivation film 11 can be more assuredly prevented.

(55) The semiconductor device shown in FIG. 8 is produced by performing sequentially the steps of FIGS. 7A-7C, and then cutting (dicing) the resulting wafer W together with the sealing resin layer 4 along the dicing lines L with the use of a dicing blade (not shown) having a thickness (width) smaller than the width of the portion of the recess 120 free from the stress relieving layers 2 in the step of FIG. 7D.

(56) FIG. 9 is a sectional view for explaining the construction of a semiconductor device according to a sixth embodiment of the present invention. In FIG. 9, components corresponding to those shown in FIG. 5 will be denoted by the same reference characters as in FIG. 5.

(57) In the semiconductor device shown in FIG. 9, the semiconductor chip 1 includes an interlayer film 9 such as of silicon oxide or silicon nitride provided between the electrode pads 6 (internal interconnection) formed in the front surface of the semiconductor chip 1 and the semiconductor substrate serving as the base of the semiconductor chip 1. The groove 12 extends to below the interlayer film 9 (into the semiconductor substrate), and the stress relieving layer 2 and the sealing resin layer 4 are partly disposed in the groove 12, whereby the side surfaces of the passivation film 11 and the interlayer film 9 are covered with the stress relieving layer 2 and the sealing resin layer 4.

(58) With this arrangement, separation and cracking of the passivation film 11 and the interlayer film 9 can be prevented, which may otherwise occur due to a stress applied to a side surface of the semiconductor device.

(59) Although the side surfaces of the passivation film 11 and the interlayer film 9 are covered with the stress relieving layer 2 and the sealing resin layer 4 in the construction shown in FIG. 9, only the stress relieving layer 2 may be partly disposed in the groove 12, and the side surfaces of the passivation film 11 and the interlayer film 9 may be covered only with the stress relieving layer 2.

(60) FIG. 10 is a sectional view illustrating the construction of a semiconductor device according to a seventh embodiment of the present invention. In FIG. 10, components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1.

(61) The semiconductor device is a semiconductor device employing the WL-CSP technique, and includes a semiconductor chip 1 having a passivation film (surface protection film) 11 provided in an outermost front surface thereof, a stress relieving layer 2 provided on the passivation film 11, rewirings 3 provided on the stress relieving layer 2, a sealing resin layer 4 provided over the rewirings 3, and metal balls 5 provided on the sealing resin layer 4.

(62) The semiconductor chip 1 is of a rectangular shape as seen in plan. The semiconductor chip 1 has a looped groove 12 (passivation absent portion) provided in a peripheral edge portion of the front surface thereof as surrounding a device formation region A (a region formed with a functional device in a semiconductor substrate serving as a base of the semiconductor chip 1) as seen in plan from above. The groove 12 is recessed from a front surface of the passivation film 11 and extends to below the passivation film 11 into the semiconductor substrate serving as the base of the semiconductor chip 1. Thus, the passivation film 11 is divided into a center portion 111 and a peripheral portion 112 which are disposed on opposite sides of the groove 12. The center portion 111 completely covers the device formation region A (formed with the functional device), and the peripheral portion 112 is spaced a predetermined distance from the periphery of the center portion 111 as surrounding the center portion 111.

(63) The passivation film 11 is composed of silicon oxide or silicon nitride. The passivation film 11 has pad openings 113 through which parts of an internal interconnection of a metal such as aluminum provided in the front surface of the semiconductor chip 1 are exposed as electrode pads 6.

(64) The stress relieving layer 2 is adapted to absorb and relieve a stress applied to the semiconductor device. The stress relieving layer 2 is composed of, for example, polyimide, and has a rectangular shape which is slightly smaller than the center portion 111 of the passivation film 11 as seen from above. Further, the stress relieving layer 2 has through-holes 21 provided at positions opposed to the respective electrode pads 6 as extending therethrough.

(65) The rewirings 3 are composed of a metal material such as copper. The rewirings 3 are respectively connected to the electrode pads 6 through the through-holes 21. The rewirings 3 are provided on a front surface of the stress relieving layer 2 as extending to positions opposed to the respective metal balls 5 with the intervention of the sealing resin layer 4.

(66) The sealing resin layer 4 is composed of, for example, an epoxy resin, and seals the front side of the semiconductor chip 1. The sealing resin layer 4 covers front surfaces of the center portion 111 of the passivation film 11, the stress relieving layer 2 and the rewirings 3, and further extends from the front surfaces to side surfaces of these layers to completely fill the groove 12 of the semiconductor chip 1. The sealing resin layer 4 has a flat front surface, and side surfaces flush with side surfaces of the semiconductor chip 1. Thus, the semiconductor device has a generally rectangular solid shape which has a size equivalent to the size of the semiconductor chip 1 as seen in plan.

(67) Flat cylindrical posts 7 of a metal such as copper are respectively provided between the rewirings 3 and the metal balls 5 as extending through the sealing resin layer 4. The rewirings 3 are respectively connected to the metal balls 5 via the posts 7.

(68) The metal balls 5 serve as external connection terminals for connection (external connection) to a wiring board not shown, and are formed of a metal material such as solder as having a ball-like shape.

(69) With the aforesaid arrangement, the passivation film 11 includes the center portion 111 completely covering the device formation region A and the peripheral portion 112 spaced the predetermined distance from the periphery of the center portion 111 as surrounding the center portion 111. In other words, the looped groove 12 is provided in the outermost front surface of the semiconductor chip 1 as surrounding the device formation region A as seen in plan from above, and the passivation film 11 is divided into the center portion 111 and the peripheral portion 112 which are respectively disposed inward and outward of the groove 12. Therefore, even if separation or cracking of the passivation film 11 occurs on the side surface of the semiconductor device, the separation and the cracking can be confined in the peripheral portion 112 of the passivation film 11. As a result, separation and cracking of the center portion 111 of the passivation film 11 are prevented, so that malfunction of the functional device can be prevented which may otherwise occur due to the separation and the cracking.

(70) Further, the side surfaces of the center portion 111 of the passivation film 11 are covered with a portion of the sealing resin layer 4 disposed in the groove 12 located between the center portion 111 and the peripheral portion 112. Therefore, the side surfaces of the center portion 111 of the passivation film 11 can be protected by the sealing resin layer 4, so that the separation and cracking of the center portion 111 can be more assuredly prevented.

(71) FIGS. 11A-11D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 10. First, a wafer W formed with a plurality of semiconductor chips 1 and having a passivation film 11 provided in an outermost front surface thereof is prepared. As shown in FIG. 11A, pad openings 113 are formed in the passivation film 11 for exposing electrode pads 6, and then stress relieving layers 2 and rewirings 3 are formed in this order on the passivation film 11.

(72) The stress relieving layers 2 are not present on dicing lines L defined between the semiconductor chips 1. Therefore, the stress relieving layers 2 disposed on adjacent ones of the semiconductor chips 1 on opposite sides of each of the dicing lines L are spaced a predetermined distance from each other, so that the passivation film 11 is partly exposed along the dicing line L between the stress relieving layers 2.

(73) In turn, as shown in FIG. 11B, grooves 12 are formed on the opposite sides of the dicing line L, so that portions of the passivation film 11 are removed from zones each extending alongside the dicing line L and spaced a predetermined distance from the dicing line L. The formation of the grooves 12 is achieved by a half-cutting process for half-cutting the resulting wafer from the front side of the passivation film 11 with the use of a blade (not shown), or by a laser machining process. Where the blade is used, the width and the depth of the grooves 12 are controlled by the thickness of the blade and a cut amount.

(74) Thereafter, as shown in FIG. 11C, a sealing resin layer 4 is formed over the entire surface of the resulting wafer W. The formation of the sealing resin layer 4 is achieved by applying an uncured epoxy resin over the entire surface of the wafer W and curing the applied epoxy resin. At this time, the uncured epoxy resin partly flows into the grooves 12 and cured in the grooves 12, thereby providing a structure such that the sealing resin layer 4 is partly disposed in the grooves 12 of the semiconductor chips 1. After posts 7 are formed at predetermined positions in the sealing resin layer 4, metal balls 5 are formed on the respective posts 7. The formation of the posts 7 is achieved by forming through-holes in the sealing resin layer 4 and supplying a metal material into the through-holes to fill the through-holes by electroplating.

(75) In turn, as shown in FIG. 11D, the resulting wafer W is cut (diced) together with the sealing resin layer 4 along the dicing lines L with the use of a dicing blade (not shown). Thus, the semiconductor device shown in FIG. 10 is provided.

(76) FIG. 12 is a sectional view illustrating the construction of a semiconductor device according to an eighth embodiment of the present invention. In FIG. 12, components corresponding to those shown in FIG. 10 will be denoted by the same reference characters as in FIG. 10.

(77) In the semiconductor device shown in FIG. 12, the stress relieving layer 2 provided on the passivation film 11 is partly disposed in the groove 12 between the center portion 111 and the peripheral portion 112 of the passivation film 11. The sealing resin layer 4 extends to the side surfaces of the stress relieving layer 2 to cover the side surfaces of the stress relieving layer 2.

(78) With this arrangement, the passivation film 11 is divided into the center portion 111 and the peripheral portion 112 which are respectively disposed inward and outward of the groove 12 as in the semiconductor device shown in FIG. 10. Therefore, even if separation or cracking of the passivation film 11 occurs on a side surface of the semiconductor device, the separation and the cracking can be confined in the peripheral portion 112 of the passivation film 11. As a result, separation and cracking of the center portion 111 of the passivation film 11 are prevented, so that malfunction of the functional device can be prevented which may otherwise occur due to the separation and the cracking.

(79) Further, the stress relieving layer 2 is partly disposed in the groove 12 located between the center portion 111 and the peripheral portion 112 of the passivation film 11, and the side surfaces of the center portion 111 of the passivation film 11 are covered with a portion of the stress relieving layer 2 disposed in the groove 12. Therefore, the side surfaces of the center portion 111 of the passivation film 11 can be protected by the stress relieving layer 2. In addition, the portion of the stress relieving layer 2 disposed between the center portion 111 and the peripheral portion 112 of the passivation film 11 also absorbs a stress applied to the semiconductor device. As a result, the separation and cracking of the center portion 111 of the passivation film 11 can be more assuredly prevented.

(80) Further, the sealing resin layer 4 extends to the side surfaces of the stress relieving layer 2 to cover the side surfaces of the stress relieving layer 2. Therefore, the stress relieving layer 2 is shielded from the outside air, so that deterioration of the stress relieving layer 2 can be prevented which may otherwise occur due to moisture contained in the outside air.

(81) FIGS. 13A-13D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 12. In the production process for the semiconductor device shown in FIGS. 13A-13D, a wafer W formed with a plurality of semiconductor chips 1 and having a passivation film 11 provided on an outermost front surface thereof is first prepared. As shown in FIG. 13A, pad openings 113 are formed in the passivation film 11 for exposing electrode pads 6, and then grooves 12 are formed on opposite sides of each of dicing lines L, whereby portions of the passivation film 11 are removed from zones each extending alongside the dicing line L and spaced a predetermined distance from the dicing line L.

(82) After the formation of the grooves 12, as shown in FIG. 13B, stress relieving layers 2 each having through-holes 21 are formed on the passivation film 11. The formation of the stress relieving layers 2 is achieved by applying liquid (uncured) polyimide over the entire surface of the resulting wafer W except a region having a predetermined width on the dicing line L, and curing the applied polyimide. At this time, the liquid polyimide partly flows into the grooves 12 and cured in the grooves 12, thereby providing a structure such that the stress relieving layers 2 are partly disposed in the grooves 12 of the semiconductor chips 1.

(83) In turn, as shown in FIG. 13C, rewirings 3 and a sealing resin layer 4 are formed on the resulting wafer, and then posts 7 are formed at predetermined positions in the sealing resin layer 4. Further, metal balls 5 are formed on the respective posts 7.

(84) Then, as shown in FIG. 13D, the resulting wafer W is cut (diced) together with the sealing resin layer 4 along the dicing lines L with the use of a dicing blade (not shown). Thus, the semiconductor device shown in FIG. 12 is provided.

(85) In the construction shown in FIG. 10, the groove 12 extends into the semiconductor substrate below the passivation film 11, so that the passivation film 11 is not present in the zone extending alongside the dicing line L. However, the groove 12 may have a depth such that at least a portion of the passivation film 11 present in that zone can be removed. As shown in FIG. 14, the groove 12 may have a depth which is equivalent to the thickness of the passivation film 11. The groove 12 having such a depth can be formed by controlling a cut amount in the half-cutting process employing the blade or controlling the intensity and period of irradiation with a laser beam. Alternatively, an etching process (wet etching or dry etching) may be employed for removing only the portion of the passivation film 11 for the assured formation of the groove.

(86) However, where the interlayer film is provided below the passivation film 11 (on the semiconductor substrate), the groove 12 is preferably formed as having a depth such that a portion of the interlayer film present in the zone extending alongside the dicing line L can be removed.

(87) For example, where a semiconductor device having a multi-level structure includes a first interconnection layer 81, a first interlayer film 91, a second interconnection layer 82, a second interlayer film 92 and a passivation film 11 provided in this order on a semiconductor substrate 10 serving as a base of a semiconductor chip 1 with the first interconnection layer 81 being electrically connected to the second interconnection layer 82 through via-holes 83 formed in the first interlayer film 91 and with the second interconnection layer 82 being electrically connected to electrode pads 6 through via-holes 84 formed in the second interlayer film 92 as shown in FIG. 15, the groove 12 is preferably formed as having a depth which is not smaller than a total thickness as measured from the front surface of the passivation film 11 to a rear surface of the first interlayer film. In this case, the groove 12 not only divides the passivation film 11, but also divides the first interlayer film 91 into a center portion 911 and a peripheral portion 912 disposed outward of the center portion 911, and divides the second interlayer film 92 into a center portion 921 and a peripheral portion 922 disposed outward of the center portion 921. Therefore, even if separation or cracking of the passivation film 11, the first interlayer film 91 and/or the second interlayer film 92 occur on a side surface of the semiconductor device, the separation and the cracking can be confined in the peripheral portion 112 of the passivation film 11, the peripheral portion 912 of the first interlayer film 91 and/or the peripheral portion 922 of the second interlayer film 92. As a result, separation and cracking of the center portion 111 of the passivation film 11, the center portion 911 of the first interlayer film 91 and the center portion 921 of the second interlayer film 92 are prevented, so that malfunction of a functional device can be prevented which may otherwise occur due to the separation and the cracking.

(88) FIG. 16 is a sectional view illustrating the construction of a semiconductor device according to a ninth embodiment of the present invention. In FIG. 16, components corresponding to those shown in FIG. 1 will be denoted by the same reference characters as in FIG. 1.

(89) The semiconductor device is a semiconductor device employing the WL-CSP technique, and includes a semiconductor chip 1 having a passivation film (surface protection film) 11 provided in an outermost front surface thereof, a stress relieving layer 2 provided on the passivation film 11, rewirings 3 provided on the stress relieving layer 2, a sealing resin layer 4 provided over the rewirings 3, and metal balls 5 provided on the sealing resin layer 4.

(90) The semiconductor chip 1 includes an interconnection layer 8 and an interlayer film 9 provided, for example, between a semiconductor substrate 10 of silicon and the passivation film 11. The interconnection layer 8 is provided on the semiconductor substrate 10 as having a pattern, and the interlayer film 9 is provided on the interconnection layer 8 to cover the interconnection layer 8.

(91) The semiconductor chip 1 has a generally rectangular shape as seen in plan, and has a groove 12 provided in a peripheral edge portion of a front surface 1a thereof. The groove 12 has a triangular sectional shape which is tapered toward a rear surface 1b of the semiconductor chip 1. The groove 12 extends to below the interlayer film 9 (into the semiconductor substrate 10). Thus, side surfaces of the passivation film 11 and the interlayer film 9 are exposed in the groove 12.

(92) The passivation film 11 is composed of silicon oxide or silicon nitride, and covers the entire surface of the interlayer film 9 except for the groove 12. The passivation film 11 has pad openings 113 through which parts of an internal interconnection of a metal such as aluminum provided in the front surface of the semiconductor chip 1 are exposed as electrode pads 6. The electrode pads 6 are electrically connected to the interconnection layer 8 through via-holes 85 extending through the interlayer film 9.

(93) The stress relieving layer 2 is composed of, for example, polyimide, and is adapted to absorb and relieve a stress applied to the semiconductor device. The stress relieving layer 2 has through-holes 21 provided at positions opposed to the respective electrode pads 6 as extending therethrough.

(94) The rewirings 3 are composed of a metal material such as copper. The rewirings 3 are respectively connected to the electrode pads 6 through the through-holes 21. The rewirings 3 are provided on a front surface of the stress relieving layer 2 as extending to positions opposed to the respective metal balls 5 with the intervention of the sealing resin layer 4.

(95) The sealing resin layer 4 is composed of, for example, an epoxy resin, and seals the front surface 1a of the semiconductor chip 1. The sealing resin layer 4 covers the front surfaces of the stress relieving layer 2 and the rewirings 3. Further, the sealing resin layer 4 extends from the front surfaces into the groove 12 to completely fill the groove 12 of the semiconductor chip 1. Thus, the side surfaces of the passivation film 11 and the interlayer 9 are covered with a portion of the sealing resin layer 4 disposed in the groove 12. The sealing resin layer 4 has a flat front surface, and side surfaces flush with side surfaces 1c of the semiconductor chip 1. Thus, the semiconductor device has a generally rectangular solid shape which has a size equivalent to the size of the semiconductor chip 1 as seen in plan.

(96) Flat cylindrical posts 7 of a metal such as copper are respectively provided between the rewirings 3 and the metal balls 5 as extending through the sealing resin layer 4. The rewirings 3 are respectively connected to the metal balls 5 via the posts 7.

(97) The metal balls 5 serve as external connection terminals for connection (external connection) to a wiring board not shown, and are formed of a metal material such as solder as having a ball-like shape.

(98) FIG. 17 is an enlarged view for explaining the dimensions of the groove 12 of the semiconductor device shown in FIG. 16. The groove 12 has a width WT which is greater than 5 m and smaller than 50 m as measured within a plane containing the front surface 1a of the semiconductor chip 1. The groove 12 has a depth DT which is greater than 3 m and smaller 50 m as measured perpendicularly to the plane containing the front surface 1a of the semiconductor chip 1.

(99) Where the semiconductor chip 1 has a thickness of 490 m as measured from the front surface 1a to the rear surface 1b thereof, for example, a thickness between the deepest portion 12p of the groove 12 and the rear surface 1b of the semiconductor chip 1 is greater than 440 m and smaller than 487 m. Where the semiconductor chip 1 has a thickness of 330 m as measured from the front surface 1a to the rear surface 1b thereof, a thickness between the deepest portion 12p of the groove 12 and the rear surface 1b of the semiconductor chip 1 is greater than 280 m and smaller than 327 m.

(100) According to this embodiment, as described above, the groove 12 is provided in the peripheral edge portion of the front surface 1a of the semiconductor chip 1 throughout the periphery of the semiconductor chip 1, and the sealing resin layer 4 is partly disposed in the groove 12. Thus, side surfaces 1c of a front portion of the semiconductor chip 1 are covered with the portion of the sealing resin layer 4 disposed in the groove 12. This prevents separation and cracking of the passivation film 11 and the underlying interlayer film 9 provided in the front portion of the semiconductor chip 1.

(101) Since the width WT of the groove 12 as measured within the plane containing the front surface 1a of the semiconductor chip 1 is greater than 5 m, the portion of the sealing resin layer 4 disposed in the groove 12 sufficiently adheres to the semiconductor substrate 10 serving as the base of the semiconductor chip 1. This prevents separation of the sealing resin layer 4 from the semiconductor substrate 10. Since the width WT of the groove 12 as measured within the plane containing the front surface 1a of the semiconductor chip 1 is smaller than 50 m, the groove 12 does not reach a region of the semiconductor chip 1 formed with a functional device. Hence, there is no possibility that the functional device of the semiconductor chip 1 is damaged.

(102) Further, the depth DT of the groove 12 as measured perpendicularly to the plane containing the front surface 1a of the semiconductor chip 1 is greater than 3 m, so that at least the passivation film 11 disposed in the outermost front surface of the semiconductor chip 1 can be protected. Since the depth DT of the groove 12 as measured perpendicularly to the plane containing the front surface 1a of the semiconductor chip 1 is smaller than 50 m, the semiconductor chip 1 (semiconductor substrate 10) has a sufficient strength. In the production process for the semiconductor device, the rear surface 1b of the semiconductor chip 1 (semiconductor substrate 10) is ground by a grinder for thickness reduction of the semiconductor device. If the groove 12 is too deep, a portion of the semiconductor chip 1 between the rear surface 1b and the groove 12 is liable to be cracked when the grinder is pressed against the rear surface 1b of the semiconductor chip 1. With this arrangement, however, the depth of the groove 12 is smaller than 50 m, so that the semiconductor chip 1 has strength sufficient to prevent such cracking.

(103) FIGS. 18A-18D are sectional views illustrating the sequential steps of a production process for the semiconductor device shown in FIG. 16. In the production process for the semiconductor device shown in FIG. 16, a wafer W having an outermost front surface covered with a passivation film 11 is prepared. The wafer has an interconnection layer 8, an interlayer film 9 and via-holes 85 provided below the passivation film 11.

(104) As shown in FIG. 18A, pad openings 113 are first formed in the passivation film 11 for exposing electrode pads 6. Then, stress relieving layers 2 and rewirings 3 are formed in this order on the passivation film 11. Further, posts 7 are formed at predetermined positions (positions at which metal balls 5 are to be formed) on the rewirings 3, for example, by electroplating.

(105) The stress relieving layers 2 are not present on dicing lines L defined between the semiconductor chips 1. Therefore, the stress relieving layers 2 disposed on adjacent ones of the semiconductor chips 1 on opposite sides of each of the dicing lines L are spaced a predetermined distance from each other, so that the passivation film 11 is partly exposed on the dicing line L between the stress relieving layers 2.

(106) In turn, as shown in FIG. 18B, a recess 120 is formed along the dicing line L as extending from the front surfaces of the stress relieving layers 2 to below the interlayer film 9. The recess 120 has an inverted trapezoidal sectional shape tapered toward the rear surface 1b of the semiconductor chip 1. The formation of the recess 120 is achieved by a half-cutting process employing a blade (not shown) having a peripheral portion in a trapezoidal sectional shape conforming to the sectional shape of the recess 120, or by a laser machining process.

(107) Thereafter, as shown in FIG. 18C, a sealing resin layer 4 is formed over the entire front surface of the wafer W. The formation of the sealing resin layer 4 is achieved by applying an uncured epoxy resin over the entire front surface of the wafer W, curing the applied epoxy resin and grinding the surface of the cured epoxy resin to expose the posts 7.

(108) After the metal balls 5 are formed on the respective posts 7, as shown in FIG. 18D, the resulting wafer W is cut (diced) together with the sealing resin layer 4 along the dicing lines L with the use of a dicing blade not shown. Thus, the semiconductor device shown in FIG. 16 is provided.

(109) While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.

(110) By the production method shown in FIG. 2A-2D, for example, a semiconductor device having no groove 12 may be produced. That is, a semiconductor device in which no groove 12 is provided and the passivation film 11 has side surfaces covered with the sealing resin layer 4 is provided by removing only a part of the passivation film 11 by controlling the cut amount in the half-cutting process employing the blade or controlling the intensity and period of the irradiation with the laser beam in the step shown in FIG. 2B.

(111) Further, the present invention is applicable not only to the semiconductor devices employing the WL-CSP technique but also to a semiconductor device adapted to be mounted on a mount board with a front surface of a semiconductor chip thereof being opposed to the mount board and with a rear surface of the semiconductor chip thereof being exposed (for bare chip mounting).