A sensor chip package assembly and an electronic device having the sensor chip package assembly are disclosed, where the sensor chip package assembly includes: a metal substrate (100) which has a bonding pad region (11) and a placement region (12), the bonding pad region having a plurality of metal bonding pads (13); a sensor chip (200) which is located on an upper surface of the metal substrate, and the sensor chip having a plurality of sensor chip bonding pads (21); an electrical connection assembly (300) which electrically connects a metal bonding pad and a sensor chip bonding pad; and a packaging material cover (400) which covers the metal substrate, the sensor chip and the electrical connection assembly, where any two adjacent metal bonding pads are spaced in an insulated manner by the packaging material cover.

A semiconductor device according to an embodiment includes: a die pad including an upper surface; a semiconductor chip provided on the upper surface, the semiconductor chip including a rectangular shape, and the semiconductor chip including an element region, and a termination region surrounding the element region; a first electrode provided on the semiconductor chip; a second electrode provided on the semiconductor chip; a first connector provided above the termination region, the first connector including a portion covering each of the four sides of the rectangular shape when viewed from above, and the first connector being electrically connected to the first electrode; and a sealing resin sealing a periphery of the semiconductor chip and the first connector.

Memory devices are disclosed. A memory device may include a command and address (CA) interface region including a first CA input circuit configured to generate a first CA output AND a second CA input circuit configured to generate a second CA output. The first CA input circuit and the second CA input circuit are arranged in a mirror relationship. The CA interface region further includes a swap circuit configured to select one of the first CA output and the second CA output for a first internal CA signal and select the other of the first CA output and the second CA output for a second internal CA signal. Memory systems and systems are also disclosed.

An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.

A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate, wherein the diode chip is electrically connected antiparallel to the semiconductor switch chip; wherein the semiconductor switch chip is electrically connected via bond wires to an emitter conductor on the substrate plate providing a first emitter current path, which emitter conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; wherein a gate electrode of the semiconductor switch chip is electrically connected via a bond wire to a gate conductor on the substrate plate providing a gate current path, which gate conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; and wherein a protruding area of the emitter conductor runs besides the diode chip towards the first semiconductor switch chip and the first semiconductor switch chip is directly connected via a bond wire with the protruding area providing an additional emitter current path running at least partially along the gate current path. The semiconductor switch chip is a first semiconductor switch chip and the diode chip is a first diode chip, which are arranged in a first row. The semiconductor module comprises further a second row of a second semiconductor switch chip and a second diode chip attached to the collector conductor, wherein the diode chip of each row is electrically connected antiparallel to the semiconductor switch chip of the same row and the first and second rows are electrically connected in parallel. The first semiconductor switch chip is arranged besides the second diode chip and the second semiconductor chip is arranged besides the first diode chip.

Embodiments of a packaged semiconductor device with interior polygon pads are disclosed. One embodiment includes a semiconductor chip and a package structure defining a rectangular boundary and having a bottom surface that includes interior polygonal pads exposed at the bottom surface of the package structure and located on a centerline of the bottom surface of the package structure and edge polygonal pads exposed at the bottom surface of the package structure, located at an edge of the rectangular boundary, and including one edge polygonal pad in the vicinity of each corner of the rectangular boundary. The interior polygonal pads are configured such that a line running between at least one vertex of each of the interior polygonal pads is parallel to an edge of the rectangular boundary of the package structure.

A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Electrode pads disposed on a first surface of a semiconductor element include a first pad located close to a corner and a second pad located apart from the corner compared with the first pad. A first wire connected to the first pad has a smaller Young's modulus than a second wire connected to the second pad. A thickness of an intermetallic compound layer formed by the first wire and the first pad is larger than a thickness of an intermetallic compound layer formed by the second wire and the second pad.