Integrated circuits are packaged by placing a plurality of semiconductor dies on a support substrate, each one of the semiconductor dies having a plurality of terminals at a side facing the support substrate and covering the semiconductor dies with a molding compound to form a molded structure. The support substrate is then removed from the molded structure to expose the side of the semiconductor dies with the terminals, and a metal redistribution layer is formed on the molded structure and in direct contact with the terminals of the semiconductor dies and the molding compound. The redistribution layer is formed without first forming a dielectric layer on a side of the molded structure with the terminals of the semiconductor dies. A corresponding molded substrate and individual molded semiconductor packages are also disclosed.

A method of fabricating a package module includes placing a pin frame having plural pins on a circuit substrate; bonding the pins to corresponding bonding areas on a circuit substrate, thereby connecting the pins to the bonding areas; cutting off a connecting portion of the pin frame; and bending the pins to be vertical to the circuit substrate. By placing the pins on the corresponding bonding areas on the circuit substrate through the pin frame, and then cutting off the connecting portion of the pin frame and bending the pins, the efficiency of assembling the package module can be greatly promoted.

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

An apparatus includes a wafer portion and a plurality of die fabricated in the wafer portion in a defined pattern such that the die are separated from each other by a dicing area or a street. The apparatus includes a conductive connection between given adjacent die. The conductive connection is electrically coupled to circuitry disposed on the given adjacent die.

A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.

A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.

A semiconductor package includes a substrate; and first and second semiconductor chips sequentially disposed on the substrate so that active surfaces of the first and second semiconductor chips face each other, wherein the first and second semiconductor chips are center pad-type semiconductor chips each having I/O pads arranged in two columns to be adjacent to a central line thereof, and I/O pads of the second semiconductor chip are electrically connected directly to the substrate without intersecting the central line of the second semiconductor chip.

Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.

An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.

A light-emitting device includes: a package defining a recess; a light-emitting element mounted on surface that defines a bottom of the recess; and a sealing member disposed in the recess so as to cover the light-emitting element and made of a light-transmissive resin that contains a filler with an average particle diameter of 200 nm or more and 500 nm or less. The sealing member comprises a filler-containing layer, which contains the filler, and a light-transmissive layer that are layered in an order from a bottom side of the recess. The filler-containing layer has a thickness of equal to or larger than a height of the light-emitting element.