High-frequency device including high-frequency switching circuit

Abstract

A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.

Claims

1. A high-frequency device having a switching circuit, the high-frequency device comprising: a first substrate; a second substrate on the first substrate; an active region on a first surface of the second substrate, the first surface facing away from the first substrate; a switching circuit within the active region; an electrode directly on the second substrate, the electrode being isolated from the switching circuit at least on the first surface of the second substrate; a terminal on, but insulated from, the second substrate; a resistor in the second substrate and connected to the electrode and the terminal; and a voltage source, wherein, the electrode is not connect to a ground potential, and the electrode is in direct contact with the second substrate such that a positive voltage signal from the voltage source can be applied to the second substrate via the terminal, the resistor, and the electrode.

2. The device of claim 1, wherein the second substrate includes a non-active region formed by ion implantation.

3. The device of claim 1, wherein the second substrate includes a non-active region formed by etching.

4. The device of claim 1, wherein the second substrate includes a non-active region and the electrode is located within the non-active region.

5. The device of claim 1, wherein the second substrate includes: a non-active region; and a field effect transistor in the switching circuit; an impurity-doped region in the non-active region, the impurity-doped region having a conductivity type the same as that of a channel of the field effect transistor wherein, the electrode is in contact with the impurity-doped region.

6. The device of claim 1, further comprising a metal plate located between the second substrate and the first substrate, the metal plate being attached to the second substrate, and the metal plate being connected to the electrode.

7. The device of claim 1, wherein the second substrate is a GaAs substrate.

8. A device comprising: a first substrate; a second substrate on the first substrate, the second substrate having an active region; an electrode on the second substrate; a resistor in the second substrate and electrically coupled to the electrode; a terminal on, but insulated from, the second substrate; a switching circuit located on a first surface of the second substrate, the first surface facing away from the first substrate; and a voltage power source, wherein, the electrode is isolated from the switching circuit at least on the first surface of the second substrate, the electrode is not connected to ground, and the electrode is in direct contact with the second substrate such that a positive voltage signal from the voltage power source can be applied to the second substrate via the terminal, resistor, and electrode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of a device according to an embodiment of the present invention;

(2) FIG. 2 is a schematic fragmentary cross-sectional view of a device according to an embodiment of the present invention;

(3) FIG. 3 is a schematic fragmentary cross-sectional view of a device according to another embodiment of the present invention;

(4) FIG. 4 is a schematic fragmentary cross-sectional view of a device according to another embodiment of the present invention;

(5) FIG. 5 is a schematic fragmentary cross-sectional view of a device according to another embodiment of the present invention;

(6) FIG. 6 is a schematic fragmentary cross-sectional view of a device according to another embodiment of the present invention;

(7) FIG. 7 is a schematic fragmentary cross-sectional view of a device according to another embodiment of the present invention;

(8) FIG. 8 is a schematic plan view of a device according to another embodiment of the present invention;

(9) FIG. 9 is a graph showing the dependence of the OFF capacitance of a field-effect transistor on voltage applied to a substrate of a device according to an embodiment of the present invention;

(10) FIG. 10 is an illustration of a distortion measurement on a known device and a device according to an embodiment of the present invention;

(11) FIG. 11 is a table showing distortion measurement results of the known device and the device according to the embodiment of the present invention;

(12) FIG. 12 is a circuit diagram of a high-frequency switching circuit;

(13) FIG. 13 is a schematic cross-sectional view of a known switch MMIC; and

(14) FIG. 14 is a schematic cross-sectional view of a field-effect transistor constituting a known switching circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

(15) A high-frequency device including a switching circuit according to an embodiment of the present invention will be exemplified. It is understood that the present invention is not limited to the embodiment.

(16) FIG. 1 is a block diagram of a device according to the embodiment of the present invention. FIG. 2 is a schematic fragmentary cross-sectional view of the device.

(17) In the present invention, a switching circuit 11 including a FET1 that is a high-electron-mobility transistor (HEMT), a junction field-effect transistor, or the like is disposed on a compound semiconductor substrate 1 composed of GaAs or the like. In this embodiment, the switching circuit 11 and a logic circuit 12 for controlling the switching circuit 11.

(18) An insulating portion 2 is disposed on the back surface of the GaAs compound semiconductor substrate 1, i.e., the insulating portion 2 is disposed on a main surface opposite a main surface at which the field-effect transistor is disposed. In this embodiment, the insulating portion 2 is an insulating package substrate 20 composed of, for example, a glass epoxy resin of flame retardant type 4 (FRT4).

(19) The package substrate 20 includes, for example, first and second input/output terminals I/O1 and I/O2 and a ground terminal GND, which are used for the switching circuit 11; and control signal input terminals CTL1 and CTL2 and a power terminal Vdd, which are used for the logic circuit 12.

(20) The compound semiconductor substrate 1 includes, for example, a high-frequency device containing the switching circuit 11 having the same circuit structure as that shown in FIG. 12 and the logic circuit 12 for driving the switching circuit 11.

(21) In the present invention, the compound semiconductor substrate 1 includes a voltage-applying electrode 30 for applying a predetermined positive voltage to the compound semiconductor substrate 1. A predetermined positive voltage from the power terminal Vdd is applied to the voltage-applying electrode 30. In this case, preferably, a resistor R is disposed between the power terminal Vdd and the voltage-applying electrode 30 to intercept an alternating current component when the voltage is applied to the voltage-applying electrode 30.

(22) For example, a power supply connection terminal 33 is disposed on an insulating surface layer 34 on the compound semiconductor substrate 1. The power supply connection terminal 33 is connected to the power terminal Vdd with a lead wire or the like. The resistor R is formed as a circuit element in the compound semiconductor substrate 1 and is disposed between the power supply connection terminal 33 and the voltage-applying electrode 30.

(23) As described above, the switching circuit 11 includes first and second FET1 and FET2 on the common compound semiconductor substrate 1, for example, a GaAs substrate, the FET1 and FET2 each being a HEMT or a J-FET. The source of the first FET1 is connected to the drain of the second FET2. One end of the current channel of the first FET1 is connected to a first input/output terminal I/O1 with a capacitor C1, the other end is connected to a second input/output terminal I/O2 via a capacitor C2. One end of the current channel of the second FET2 is connected to a ground terminal GND via a capacitor C3. Thereby, the circuit is DC-decoupled from the exterior.

(24) Gates of the first and second FET1 and FET2 are connected to control signal input terminals CTL1 and CTL2 via resistor R1 and R2, respectively, the signal input terminals CTL1 and CTL2 receiving control signals from the logic circuit 12. The midpoint of the current channel between the source of the first FET1 and the drain of the second FET2 is connected to a DC bias terminal via a resistor R3.

(25) The logic circuit 12 is supplied with a voltage from the power terminal Vdd to which a power supply voltage is applied. Control signals from control signal terminals CTLa and CTLb are fed to the logic circuit 12. The logic circuit 12 feeds predetermined control signals to the control signal input terminals CTL1 and CTL2. The logic circuit 12 feeds a predetermined bias voltage to a bias terminal Bias.

(26) The above-described circuit elements, i.e., the switching circuit 11 and the logic circuit 12, are disposed on a main surface of the active region 1a of the compound semiconductor substrate 1. The active region 1a can be formed by ion implantation.

(27) The first field-effect transistor FET1 is exemplified in FIG. 2. The field-effect transistor is formed by the following procedure: for example, a p-type gate region 5 or the like is formed on a channel-forming region 4 having low impurity concentration by ion implantation or the like. An n-type source or drain 3 is similarly formed by ion implantation or the like so as to be disposed at each side of the channel-forming region 4.

(28) A resin mold package 40 covers the compound semiconductor substrate 1 and the like disposed on the package substrate 20.

(29) The switching circuit 11 having the structure is controlled by a signal from the logic circuit 12 and operates in the same way as described in FIG. 12.

(30) That is, for example, a bias voltage of 2 V from the logic circuit 12 is applied to the switching circuit 11 via the resistor R3. For example, when a high voltage, e.g., 3 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1 is 1 V. As a result, the FET1 is ON. On the other hand, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2 is −2 V. As a result, the FET2 is OFF. Therefore, the channel between the terminals I/O1 and I/O2 is ON, that is, the switching circuit 11 is ON.

(31) In contrast, for example, when a low voltage, e.g., 0 V, is applied to the terminal CTL1, the gate bias (with respect to the drain and source) of the first FET1 is −2 V. As a result, the FET1 is OFF. On the other hand, for example, when a high voltage, e.g., 3 V, is applied to the terminal CTL2, the gate bias (with respect to the drain and source) of the second FET2 is 1 V. As a result, the FET2 is ON. Therefore, the channel between the terminals I/O1 and I/O2 is OPEN. That is, the signal channel is high-frequency-short-circuited, thus ensuring further isolation.

(32) In the present invention, as described above, the voltage-applying electrode 30 is disposed on the compound semiconductor substrate 1 in order to apply, for example, a predetermined positive bias voltage to the compound semiconductor substrate 1. This results in a high-frequency device including a switching circuit having improved distortion.

(33) This is believed to result from a decrease in capacitance due to the reduction of the depletion region of the field-effect transistor. For example, this is believed to result from the prevention of the capture and release of an unstable electric charge by a trap or the like.

(34) In the embodiment shown in FIG. 2, the voltage-applying electrode 30 is disposed on a main surface having the circuit elements, such as a FET, of the compound semiconductor substrate 1. Alternatively, as shown in FIG. 3 that is a schematic fragmentary cross-sectional view of a high-frequency device including a switching circuit according to an embodiment of the present invention, the voltage-applying electrode 30 may be constituted of first and second electrodes 31 and 32 that are electrically connected to each other.

(35) In this case, a resistor R may be disposed between the first and second electrodes 31 and 32. Alternatively, the above-described resistor R may be disposed between the first electrode 31 and the power supply connection terminal 33.

(36) As shown in FIG. 3, the first electrode 31 is disposed on one main surface having circuit elements, such as a FET, of the compound semiconductor substrate 1. The second electrode 32 is disposed on the other main surface. A positive voltage can be applied to the compound semiconductor substrate 1 using the second electrode 32.

(37) As shown in FIG. 3, the first electrode 31 may be electrically connected to the second electrodes 32 through a via hole 50 passing through the compound semiconductor substrate 1.

(38) Alternatively, the first electrode 31 may be electrically connected to the second electrodes 32 with lead wires.

(39) In the structure shown in FIG. 3, the second electrode 32 is disposed under at least a region at which field-effect transistors, such as FET1 and FET2, are disposed. However, a larger area of the second electrode 32 results in larger parasitic capacitance, thereby possibly affecting high-frequency characteristics. Thus, the area of the second electrode 32 is preferably 50% or less of that of the compound semiconductor substrate 1.

(40) FIG. 4 is a schematic cross-sectional view of a device according to another embodiment of the present invention. In this embodiment, a metal plate is disposed between the compound semiconductor substrate and the insulating portion 2.

(41) In this embodiment, a metal plate 60, which is a lead frame, is disposed. A die pad 61 of the lead frame is electrically connected to the back surface of the compound semiconductor substrate 1 shown in FIG. 2 with a conductive material 62, such as a silver paste. The resin mold package 40 functions as the insulating portion 2. In this case, the voltage-applying electrode 30 may be connected to the power terminal Vdd via the die pad 61 and the above-described resistor R.

(42) In FIGS. 3 and 4, the same or equivalent elements corresponding to FIGS. 1 and 2 are designated using the same reference numerals, and redundant description is not repeated.

(43) FIGS. 5, 6, and 7 are each a schematic cross-sectional view showing an exemplary positional relationship between a field-effect transistor (FET) and the voltage-applying electrode 30. Each exemplified FET is a junction-gate pseudomorphic high-electron-mobility transistor (PHEMT). That is, the compound semiconductor substrate 1 provided with epitaxially grown semiconductor layers constituting the PHEMT is disposed on a semi-insulating (SI) GaAs substrate 1S or the like.

(44) As shown in each of FIGS. 5, 6, and 7, for example, an undoped buffer layer 71 composed of AlGaAs, a first n-type-impurity-doped layer 72, a channel layer 73, a second n-type-impurity-doped layer 74, and a lightly doped layer 75 are formed in that order by epitaxial growth on the GaAs substrate 1S. A p-type gate region 76 is formed by ion implantation of Zn ions or the like.

(45) Contact layers 78, which are each an n-type heavily doped source/drain composed of GaAs or the like, are disposed between the p-type gate region 76. Electrodes 79 are disposed on the respective contact layers 78. Thereby, the FET, which is HEMT, is formed.

(46) In addition to the active region 1a including the circuit elements such as the FET, a high-resistivity nonactive region 1b formed by ion implantation of boron B is disposed so as to surround the active region 1a or to separate a plurality of active regions.

(47) As shown in FIG. 5 or 7, the voltage-applying electrode 30 may be disposed on the nonactive region 1b. Alternatively, as shown in FIG. 6, which is a schematic cross-sectional view, the voltage-applying electrode 30 may be disposed on another active region 1a separated from the active region 1a including the FET by the nonactive region 1b.

(48) The voltage-applying electrode 30 is in contact with an impurity-doped region 77 of the same conductivity type as that of the channel (channel-forming region) or the same conductivity type as that of the gate.

(49) In this structure, it was confirmed that distortion characteristics and isolation were further stabilized and improved. This is believed to result from the successful application of a positive voltage to the back side of the FET.

(50) The impurity-doped region 77 can be formed simultaneously with, for example, the formation of the p-type gate region 76 of the FET, such as the HEMT, or the contact layers 78, which are each a source/drain.

(51) In the above-described embodiment, the nonactive region 1b is formed by ion implantation. Alternatively, the active region 1a may be formed in a high-resistivity semiconductor layer by ion implantation depending on the structure of the FET.

(52) In each of the above-described embodiments, the switching circuit 11 and the logic circuit 12 are disposed on the common compound semiconductor substrate 1. Alternatively, as shown in FIG. 8, which is a schematic plan view, a high-frequency device having the following structure may be formed: for example, only the switching circuit 11 is disposed on the GaAs compound semiconductor substrate 1. A logic circuit is disposed on, for example, a Si substrate, which is a Group IV element semiconductor substrate, different from the compound semiconductor substrate 1. The switching circuit 11 is connected to the logic circuit with lead wires or the like. In FIG. 8, the same or equivalent elements are designated using the same reference numerals, and redundant description is not repeated.

(53) FIG. 9 is a graph showing the dependence of the OFF capacitance of the field-effect transistor FET1 on bias voltage applied to the compound semiconductor substrate 1. In this case, it is found that the OFF capacitance is reduced by 10% when a voltage of 3 V is applied to the substrate.

(54) That is, with respect to switching properties, isolation is improved.

(55) The device shown in FIG. 3 is a high-frequency device having a dual pole dual throw (DPDT) switch. In this case, intermodulation distortions IMD2 and IMD3 are significantly improved.

(56) As shown in FIG. 10, high-frequency input signals RF2 and RF1 are fed to a dual pole 3 throw (DP3T) switching circuit between input/output terminals I/O1 and I/O2. FIG. 11 shows second- and third-order intermodulation distortions in an inventive example, in which a voltage is applied to a substrate, and a related example, in which a voltage is not applied to a substrate. As is clear from the results, in the inventive example, the intermodulation distortions are improved.

(57) As described above, a high-frequency device, corresponding to 3G, according to the embodiment of the present invention meets the stringent requirements, i.e., has improved high-frequency characteristics, in particular, reduced distortion.

(58) The present invention is not limited to the above-described embodiments.

(59) It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.