In an elastic wave filter apparatus, IDT electrodes and first and second electrode lands are provided on a first main surface of a piezoelectric substrate. The piezoelectric substrate, a supporting layer, and a covering member define a hollow portion. A signal terminal, a ground terminal, and a heat diffusion layer are provided on a second main surface of the piezoelectric substrate. The first and second electrode lands are electrically connected by first and second connection electrodes to the signal terminal and the ground terminal, respectively. The heat diffusion layer is provided at a position where the heat diffusion layer overlaps at least a portion of the IDT electrodes across the piezoelectric substrate.

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, several metal wires electrically connected to the substrate and the sensor chip, a translucent layer corresponding in position to the sensor chip, and an adhesive. A top surface of the sensor chip has a sensing region and a spacing region around the sensing region. The sensor chip includes several connecting pads arranged on a first portion of the top surface between the first edge and the spacing region, and a second portion of the top surface between the second edge and the spacing region is provided without any connecting pad. The width of the first portion is greater than that of the second portion. The adhesive covers the surrounding side of the sensor chip, the first portion, and the surrounding side of the translucent layer. Part of each metal wire is embedded in the adhesive.

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, several metal wires electrically connected to the substrate and the sensor chip, a translucent layer corresponding in position to the sensor chip, a combining layer firmly fixing the translucent layer to the sensor chip, and a packaging compound. A top surface of the sensor chip has a sensing region and a spacing region around the sensing region. The sensor chip includes several connecting pads arranged on the top surface between at least part of the edges thereof and the spacing region. The translucent layer has a fixing region arranged outside a portion thereof adhered to the combining layer. The packaging compound covers the fixing region and the external sides of the sensor chip, the combining layer, and the translucent layer. Each metal wire is embedded in the combining layer and the packaging compound.

In one example, an electronic device can comprise (a) a first substrate comprising a first encapsulant extending from the first substrate bottom side to the first substrate top side, and a first substrate interconnect extending from the substrate bottom side to the substrate top side and coated by the first encapsulant, (b) a first electronic component embedded in the first substrate and comprising a first component sidewall coated by the first encapsulant, (c) a second electronic component coupled to the first substrate top side, (d) a first internal interconnect coupling the second electronic component to the first substrate interconnect, and (e) a cover structure on the first substrate and covering the second component sidewall and the first internal interconnect. Other examples and related methods are also disclosed herein.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

Semiconductor three-dimensional integrated circuit packages and methods of forming the same are disclosed herein. A method includes bonding a semiconductor chip package to a substrate and depositing a thermal interface material on the semiconductor chip package. A thermal lid may be placed over and adhered to the semiconductor chip package by the thermal interface material. The thermal lid includes a wedge feature interfacing the thermal interface material. The thermal lid may be adhered to the semiconductor chip package by curing the thermal interface material.

Stacked semiconductor die assemblies having memory dies stacked between partitioned logic dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a first logic die, a second logic die, and a thermally conductive casing defining an enclosure. The stack of memory dies can be disposed within the enclosure and between the first and second logic dies.

According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM1) between the heat spreader and the heat source.

Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.

In some examples, a package comprises a semiconductor die having a first surface and a second surface opposing the first surface, the semiconductor die including circuitry formed in the first surface. The package includes an acoustic waveguide in the semiconductor die, the acoustic waveguide including an array of capacitors. The array of capacitors includes a transducer portion and a diffraction grating portion. The transducer portion is configured to convert signals between electrical signals and acoustic waves, and the diffraction grating portion is configured to direct the acoustic waves toward and receive the acoustic waves from the second surface.